Advanced Micro Devices, the world’s second largest maker of x86 central processing units, and SimpleTech, a leading maker of memory modules, said that they would collaboratively define the standard for registered DDR3 memory modules for next-generation servers and workstations. The announcement may indicate that AMD is heading the development of a standard that may become a competitor to the fully-buffered DIMMs, as the new modules solve the density issues of the DDR2 memory.
“AMD and SimpleTech are leading an open and collaborative effort within our industry to drive DDR3 along a seamless upgrade path, combined with a step function improvement in performance-per-watt characteristics,” aid Levi Murray, director of technology enabling and infrastructure development at AMD.
Densities of DDR3 RDIMMs are designed to range from 512MB to 32GB, which allows server makers to install more memory into their machines, avoiding use of fully-buffered DIMMs, which are currently pushed by Intel Corp. and some of its partners since DDR2 memory modules have certain issues when many chips and modules are used within one machine.
The work on the registered dual in-line memory modules with DDR3 chips (RDIMM DDR3) of the two companies is being conducted within JEDEC, a coalition of approximately 270 companies focused on the creation of open standards for the solid-state technology industry.
“By working collectively as a member of JEDEC, we can better ensure the benefits of this technology are fully achieved with minimal disruption, maximum investment protection and improved economic opportunities for the entire value chain,” Mr. Murray added.
The two companies had specific roles in defining the overall solution. AMD defined the timing of the interface and termination characteristics, while SimpleTech defined the register component to support standard height as well as VLP and ATCA applications. In this new design, register and PLL functions are integrated into a single device to reduce overall system power consumption. In addition to including control words that permit device configuration and allow vendors to add new functions over time, SimpleTech also initiated the inside-out dual fly-by signaling approach used for all DDR3 RDIMM layouts.
“AMD’s collaboration on the development of the DDR3 RDIMM architecture and design was essential to a successful solution. AMD's input during the definition phase and participation in developing the RDIMM and defining the SPD configuration EEPROM drove progress forward,” said Bill Gervasi, vice president of DRAM technology at SimpleTech.
Initialization scheme, parity function as well as control registers were approved by JEDEC in March. Validation is under way, testing is expected to begin in 2007 and full production is planned by 2008.