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Samsung Electronics, the world’s largest producer of memory chips, said it had developed 50nm DDR2 dynamic random access memory (DRAM) device that incorporates three-dimensional transistor design. The new chip mainly showcases Samsung’s abilities to develop advanced technology ahead of the rivals.

“With the 50nm DRAM development, we’re continuing our technology leadership, paving the way for our customers to reap not only greater cost efficiencies but also to make superior products,” said Nam Yong Cho, executive vice president of memory sales and marketing at Samsung Electronics’ Semiconductor business.

The new 1Gb memory chip from Samsung produced using 50nm process technology is 55% smaller compared to a similar device produced using 60nm fabrication process and thus is much cheaper to produce. However, Samsung says that actual production of memory chips using 50nm process technology is slated to begin in 2008, about two years from now. The significant timeframe between technology showcase and actual deployment is conditioned by the fact that the 50nm manufacturing process of Samsung incorporates several state-of-the-art features.

Key to the increased production efficiencies in the newly developed 50nm process is the use of a selective epitaxial growth transistor (SEG Tr). This 3D transistor has a broader electron channel that optimizes the speed of each chip’s electrons to reduce power consumption and enable higher performance, according to Samsung.

Continued miniaturization of the overall memory circuit and an increasingly limited area of coverage within a wafer cell make it much harder to secure and sustain sufficient volumes of electrons. Adding to the 50nm design improvements, the SEG transistor introduces a multi-layered dielectric layer (ZrO2/Al2O3/ZrO2) to resolve weak electrical features. In addition, the new dielectric layer sustains higher volumes of electron to increase storage capacity, ensuring higher reliability in storing data, the company indicated.

Further, Samsung’s proprietary RCAT (Recess Channel Array Transistor) technology also has been adapted to work well with Samsung’s 50nm DRAM process. The RCAT, which effectively doubles the refresh term of DRAM, is a critical technology supporting higher scalability for DRAM regardless of chip size – a key feature for enabling circuitry beyond 50nms.

Currently Samsung uses 80nm process technology for DDR2 memory manufacturing.

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