News
 

Bookmark and Share

(0) 

JEDEC (Joint Electron Device Engineering Council) technology association, an industry body that develops and finalizes various memory technologies, on Tuesday announced it had completed development and publication of the DDR3 (double data rate 3) memory device standard.

“The DDR3 standard represents the culmination of countless hours of collaboration between memory device, system, component and module producers.  This standard will permit emerging systems to achieve greater performance, storage and functionality, consistent with the needs of an increasingly information-intensive world community,” said Joe Macri, chairman of JEDEC JC-42.3 committee.

The statement by the technology association reads that key technology and functional improvements of DDR3 include a 1.5V power supply, increased operating temperature range, memory device reset, burst chop, dynamic on-die termination, output driver calibration, write leveling and other innovative features to enable high-speed operation and broad applicability in loose device and module applications. The DDR3 standard is intended to operate over a performance range from 800MHz to 1600MHz and device densities from 512Mb to 8Gb in monolithic and stacked packages.

In addition to the introduction of the DDR3 chip spec, JEDEC is completing publication and release of a wide range of DDR3-based memory modules, including registered DIMMs, unbuffered DIMMs, SO (small outline) DIMMs and other module types and configurations intended for use in desktop, mobile and server computer systems, telecommunications, point of sale and a wide range of other electronic products. Support devices have also been developed and include registers, PLL’s (phase locked loops) and other interface devices optimized for use with the new technology.

In conjunction with and to facilitate comprehension and adoption of the new memory standard, JEDEC is also announcing a DDR3 technical workshop, to be held in San Jose California on October 3-4, 2007. This workshop will include technical presentations by major DRAM and chipset producers, and is intended to provide adopters with a detailed understanding of the DDR3 specification, operational characteristics, changes from prior generation devices, application guidelines, an overview of JEDEC memory modules and other critical information related to this key memory technology.  Presenters will have detailed technical knowledge of the device and the JEDEC specification, and will be available to answer questions.

Discussion

Comments currently: 0

Add your Comment




Related news

Latest News

Tuesday, July 22, 2014

10:40 pm | ARM Preps Second-Generation “Artemis” and “Maya” 64-Bit ARMv8-A Offerings. ARM Readies 64-Bit Cores for Non-Traditional Applications

7:38 pm | AMD Vows to Introduce 20nm Products Next Year. AMD’s 20nm APUs, GPUs and Embedded Chips to Arrive in 2015

4:08 am | Microsoft to Unify All Windows Operating Systems for Client PCs. One Windows OS will Power PCs, Tablets and Smartphones

Monday, July 21, 2014

10:32 pm | PQI Debuts Flash Drive with Lightning and USB Connectors. PQI Offers Easy Way to Boost iPhone or iPad Storage

10:08 pm | Japan Display Begins to Mass Produce IPS-NEO Displays. JDI Begins to Mass Produce Rival for AMOLED Panels

12:56 pm | Microsoft to Fire 18,000 Employees to Boost Efficiency. Microsoft to Perform Massive Job Cut Ever Following Acquisition of Nokia