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Elpida Memory announced today that it has developed a shrunken version of its 1-gigabit DDR2 SDRAM that delivers 20% more chips from a single 300mm wafer. Volume production of the new shrunken chip is expected to begin before the end of 2008 and will be shared among Elpida's Hiroshima Plant, its Taiwan-based Rexchip joint venture and its manufacturing partner PSC.

The chip size shrink was made possible by applying new architecture to first-generation 65nm process products to achieve a reduced chip size. Using its own 65nm process that has already demonstrated high yields and productivity, Elpida estimates that costs for the shrunken version of 65nm products will be about 20% less compared to first-generation products. Moreover, as the migration to 50nm process technology leads to higher wafer processing costs due to the need for capital expenditures, Elpida believes its new 65nm process-based chip will be cost competitive with 50nm products already announced by other DRAM makers.

Also, Elpida has reached the final stage of developing a 50nm process and plans to complete work in November. The company intends to begin volume production as early as late December this year, ahead of its earlier January-March 2009 timetable. The migration to 50nm products having a chip size of below 40mm2 should further increase performance and lower costs by making it possible to improve productivity roughly 50% compared with the 65nm shrunken version.

Tags: Elpida, 65nm, 50nm

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