JEDEC, the global standards development organization for the microelectronics industry, on Thursday announced the publication of JESD209-2 LPDDR2 Low Power Memory Device Standard. The LPDDR2 is a shared interface for nonvolatile memory (NVM) and volatile memory (SDRAM), and a range of densities and speeds.  The standard enables increased memory density, improved performance, smaller size, overall reduction in power consumption as well as a longer battery life.

“Reducing power consumption, improving performance and a shared NVM/SDRAM interface will help the industry offer significant benefits to product developers and consumers,” said Mian Quddus, JEDEC Board of Directors Chairman.

In response to increasing demand for reduced power consumption by devices, the JEDEC LPDDR2 standard offers several power-saving features. LPDDR2 includes a reduced interface voltage of 1.2V from the 1.8V specification in the previous (LPDDR) memory technology, which will result in a reduction in power consumption of over 50% under similar device density and performance conditions. The standard further encompasses devices having a core voltage of 1.2V (as compared to existing 1.8V core voltage devices), further decreasing device power consumption.

In addition, LPDDR2 supports advanced mechanisms for managing power usage such as Partial Array Self Refresh and Per-Bank Refresh.  Partial Array Self-Refresh, for example, allows portions of the array to be powered down when not required, permitting applications to determine device memory requirements on a real-time usage basis. 

For the first time, a single JEDEC standard encompasses two distinct types of memory: NVM and SDRAM. The JEDEC LPDDR2 standard allows these two memory types to share a common bus interface, thereby reducing the controller pincount and facilitating increased memory package density. LPDDR2 NVM and SDRAM devices can be stacked, with a common interface, greatly simplifying memory controller and interface designs and offering space-saving opportunities to product developers. 

In the JEDEC LPDDR2 standard, multiple device configurations are supported to meet the requirements of a wide array of mobile devices, including:

• An operating frequency range from 100MHz to 533MHz
• Data widths of x8, x16 and x32
• Two pre-fetch options (2 and 4-bit) as well as both 1.8 and 1.2 Volt core voltage options
• A wide range of device densities (NVM: 64Mb-32Gb, DRAM: 64Mb-8Gb), over time

“With low power, high performance, scalability, and the ability to share a single memory interface between both Non-Volatile and Volatile memories, LPDDR2 is revolutionary in its scope and versatility, and creates a new class of low power memory devices that will help to transform the mobile industry, enabling handsets to power demanding applications such as high performance gaming and HDTV,” said Roger Isaac, chairman of JEDEC’s JC-42.6 subcommittee for low power memory.

Tags: JEDEC, LPDDDR, DRAM, Flash