Rambus, a leading developer of memory and interface technologies, this week demonstrated an XDR-based memory sub-system that ran at 7.20GHz. Rambus claims that despite of very high clock-speed, the XDR-powered system consumes 40% less power compared to GDDR5 memory sub-system.
“Future graphics and multi-core processors require significantly higher memory performance under extremely challenging power and thermal constraints. This technology demonstration highlights the outstanding power efficiency of the XDR and XDR2 memory architectures at performance levels from 3.2 to 7.2Gbps with scalability to well over 10Gbps,” said Martin Scott, senior vice president of research and technology development at Rambus.
This demonstration featured Elpida's recently-announced 7.20GHz x32 1Gb XDR DRAM device and an XIO memory controller transmitting “realistic” data patterns. Rambus has not revealed the actual bandwidth provided by the XDR-based memory sub-system, but indicated that the XIO memory controller is up to 3.5 times more power efficient than a GDDR5 controller, and the total memory system can provide is up to two times more bandwidth than GDDR5 at equivalent power.
At present, graphics cards manufacturers utilize up to 3.90GHz GDDR5 memory, which gives graphics chips 124.80GB/s of memory bandwidth in case of 256-bit memory controller. In case Rambus’ demonstration included 128-bit memory controller, the peak bandwidth would be 115.2GB/s, but in case of 256-bit memory controller the bandwidth would be whopping 230.40GB/s. It should be noted that Samsung Electronics began to produce 7.00GHz GDDR5 memory chips, which puts the industry-standard GDDR5 just a little behind proprietary XDR in terms of peak performance.
In addition, the XIO memory controller demonstrated bi-modal operation with support for both XDR DRAM as well as next-generation XDR2 DRAM.
This silicon demonstration, shown at Denali MemCon 2009 in San Jose, is the first implementation supporting the XDR memory architecture roadmap incorporating innovations developed as part of Rambus' Terabyte Bandwidth Initiative. Implemented in the bi-modal XIO memory controller for XDR2 operation, these innovations include:
- Fully Differential Memory Architecture (FDMA) - enhances signal integrity and increases performance through point-to-point differential signaling of clock, data, and command/address (C/A), an industry first;
- FlexLink C/A - reduces pin count and increases scalability;
- Enhanced FlexPhase - enables the world's highest memory signaling rates while simplifying routing and board design.
In addition, the XDR2 memory architecture includes:
- Micro-threading of the DRAM core - introduced by Rambus in early 2005, increases data transfer efficiency and reduces power consumption;
- 16X Data Rate - allows for extremely high data rates with the use of a relatively low-speed system clock.
Built on these innovations, an XDR2 memory system can provide memory bandwidths of over 500GB/s to a system-on-chip. A single 9.60GHz x32 XDR2 DRAM device can deliver up to 38.4GB/s of peak bandwidth, and the XDR2 architecture supports a roadmap to device bandwidths of over 50GB/s (~12.60GHz).
Unfortunately for Rambus, XDR is only produced by Elpida Memory and Samsung Electronics, and the only XDR-based device that can boast with mass availability is Sony PlayStation 3.