Serial Port Memory Technology (SPMT) consortium has announced the release of the SPMT specification. SPMT is the first-of-its-kind memory specification for dynamic random access memory (DRAM) based on a serial interface rather than the standard parallel interface. The technology initially targets the mobile handset market and is designed to offer high performance amid low power consumption
“The availability of the SPMT specification marks the beginning of a new era in general purpose memory technology for the mobile market. The technology defined in the specification represents a huge leap forward in providing a low cost, high bandwidth and low power solution for the rapidly evolving mobile market enabling a whole new generation of products,” said Jim Venable, president of SPMT, LLC.
The SPMT Consortium’s founding members - Hynix Semiconductor, LG Electronics, Samsung Electronics and Silicon Image – form the governing body of the organization and are, together with contributor members, responsible for developing the SPMT specification which feature:
- Pin count reduction by a minimum of 40% compared to existing DRAM technologies;
- Flexible bandwidth ranging from 200MB/s to 12.6GB/s and higher;
- Single or multiple port configurations connecting to a single SPMT-enabled memory chip.
As future generations of handsets take on more functions typically seen in laptops, and as the line between cell phones and handheld media-intensive devices blur, new memory architectures will be required to handle demands for ever greater bandwidth while keeping power low and cost down.
Rambus, a developer of memory and interconnection technologies, also started to create its own memory technology designed specifically for low-power devices. The company hopes to create 32-bit DRAMs that would work at 4.30GHz and deliver 17.2GB/s of bandwidth.
The SPMT consortium welcomes inquiries from companies and organizations interested in joining the group.