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Toshiba Corp. introduced a family of higher performance 24nm eMMC devices. The new NAND flash chips for embedded applications utilize double data rate interface and therefore provide better random access and sequential performance. Thanks to new 24nm fabrication process, the new chips are also small and thus more affordable compared to competing solutions.

The densities of Toshiba's eMMC NAND flash chips with toggle-mode DDR interface for embedded applications range from 2GB to 128GB and offer full compliance with the JEDEC e-MMC version 4.41 standard.

Integrating up to 128GB NAND and an e-MMC controller in a single package, Toshiba's new family of 24nm e-MMC devices combine up to 16 pieces of 64Gb (8GB) NAND chips fabricated with Toshiba's 24nm process technology. Toshiba was the first company to succeed in combining 16 pieces of 64Gbit die in e-MMC to achieve 128GB of memory by applying advanced chip thinning and layering technologies to realize individual chips that are only 30 micrometers thick.

Toshiba's 24nm e-MMC process lowers costs, enables higher densities, boosts performance and allows for smaller packages – all of which are key requirements for space-conscious applications such as smartphones, tablet PC s, electronic book readers, digital video cameras, printers, servers, and POS systems.

“The utilization of our new toggle-mode DDR NAND die at 64Gb density is key to enabling our eMMC to support the higher performance, and smaller, thinner packages that customers desire. For example, our 128GB e-MMC can now be supported in a smaller 14x18 package, which many space conscious applications can support," noted Scott Beekman, senior business development manager, mobile communications memory for Toshiba America Electronic Components.

Samples of 8GB, 16GB, 32GB and 64GB 24nm e-MMC product family are available now, and mass production will begin in Q3, with other densities to follow.

Tags: Toshiba, NAND, Flash, eMMC


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