Samsung Electronics, the world’s largest manufacturer of dynamic random access memory (DRAM), said that it expected standardization of multi-layer hyper memory cube (HMC) DRAM solution by late 2012 and intends to begin production of such devices in 2013. The HMC are projected to break through a critical bottleneck called “memory wall” that has been blocking full utilization of multi-core, multi-threaded CPUs.
“We anticipate that the group will complete an industry-wide spec for the 1st phase of HMC by the end of 2012. Within a year or two after that, HMC products should begin to reach the market as an alternative to DRAM in HPC and network applications,” said Jim Elliott, vice president of memory marketing at Americas.
Micron and Samsung are the founding members of the recenty formed hybrid memory cube consortium (HMCC), and will work closely with fellow developers Altera Corp., Open- Silicon and Xilinx to collectively accelerate industry efforts in bringing to market a broad set of technologies. The consortium will initially define a specification to enable applications ranging from large-scale networking to industrial products and high-performance computing.
One of the primary challenges facing the industry – and a key motivation for forming the HMCC – is that the memory bandwidth required by high-performance computers and next- generation networking equipment has increased beyond what conventional memory architectures can provide. The term “memory wall” has been used to describe the problem.
Breaking through the memory wall requires a new architecture that can provide increased density and bandwidth at significantly reduced power consumption. HMC capabilities are a leap beyond current and near-term memory architectures in the areas of performance, packaging and design efficiencies. By defining an industry interface specification for developers, manufacturers and architects, the consortium is committed to making HMC a successful new high-performance memory technology.
Intel Corp. demonstrated HMC at Intel Developer Forum in September, 2011. The Hybrid Memory Cube – which was jointly designed by Intel and Micron – demonstrates a new approach to memory design delivering a 7-fold improvement in energy-efficiency over today's DDR3. Hybrid Memory Cube uses a stacked memory chip configuration, forming a compact “cube”, and uses a new, highly efficient memory interface which sets the bar for energy consumed per bit transferred while supporting data rates of 1Tb/s (one trillion bits per second). This research technology could lead to dramatic improvements in servers optimized for cloud computing as well as ultrabooks, televisions, tablets and smartphones.