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Intel Labs, a research arm of Intel Corp., and Industrial Technology Research Institute (ITRI) of Taiwan decided to establish the Intel and ITRI Research Collaboration (IIRC). The organization will explore many areas, including future energy-efficient memory technologies.

The first project under the collaboration is focused on the future of memory technologies used in computing devices such as ultrabooks, laptops, tablets, and handhelds. By creating memories with much greater energy efficiency, these mobile devices will be better equipped to handle the data-intensive applications of the future. The new dynamic random access memory (DRAM) to be jointly developed by Intel and ITRI is expected to offer lower latencies and clock-speeds, which will increase overall performance of memory compared to that of central processing units and thus close the so-called memory gap.

While the microprocessor performance increased at the rate of roughly 50% per year, the speed of DRAM memory improved at a rate of only 7% per year. Processor architecture began to advance on several fronts to compensate for the growing gap.  Advances on one front attempted to reduce the memory access latency via caching. Caching is a very effective scheme to bring down the average memory access latency because memory access patterns exhibit spatial and temporal localities. Most of the time, an access to data or instruction hits the cache and results in a very short delay only.  Advances in architecture also worked to better tolerate memory latency through methods like out of order execution. Out of order execution allows other instructions that are not blocked by the memory access to continue to execute, thus allowing the processor to bypass any data resolution delays. Unfortunately these architectural techniques require the implementation of more complex logic circuitry, causing power consumption to increase, and this has led us to a point where the return on investment of these complex techniques is diminishing, according to Intel. Moreover, memory has been aiming at density reduction only. There have been few corresponding architectural techniques to improve performance on the memory side.

Besides performance, power consumption is becoming a very important criterion for system design. High power consumption complicated the thermal solution and increases the operation cost of a computer system. Intel must include the operational cost into the total cost of the computer and not just the system hardware cost.  Today, it is estimated that memory accounts for 20% to 40% of a computer system’s total power. The proportion is increasing as the density and performance requirements of DRAM increase. One example is the over-fetching incurred due to the way current DRAM die is organized. It activates thousands of bits with each request, but only returns a small number of data bits to the processor. Another example of the DRAM energy inefficiency comes from the fact that DRAM dies are put together on a DIMM and multiple DIMMs may share a channel to communicate with the processor.  A single request must activate multiple dies and drive more than one load. Moreover, DRAM also needs to be refreshed periodically to ensure that data is retained in the memory devices.  The DRAM consumes power even though there is no actual data activity. This is bad for laptop, tablet and handheld platforms because users want instant on from standby and for standby to last for multiple days between charges.

“We are starting a memory research project with the Industrial Technology Research Institute (ITRI) of Taiwan to address the performance gap and to reduce the power consumption of memory. Novel techniques are being investigated to extend DRAM refresh time to reduce standby power. We are also looking into using an extra (vertical) dimension to help reduce the physical distance between data transfers to save even more energy. Allowing DRAM dies to stack on each other opens up many new opportunities for architectural improvement. We will build models and utilize simulation to explore the design space holistically to find the highest performance, lowest power solution possible. A prototype is planned as well to demonstrate our research results,” explained Shih-Lien Lu, a senior principal engineer from Intel Labs.

ITRI was proposed as a potential partner due to its close ties to industry, including memory design houses, foundries as well as leading computing device OEMs & ODMs, and a proven record of making an impact with their research. For example, ITRI helped to establish the semiconductor foundry industry with spin-outs such as TSMC.

Tags: Intel, ITRI, DRAM, DDR3, DDR4

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Comments currently: 1
Discussion started: 12/08/11 10:24:35 AM
Latest comment: 12/08/11 10:24:35 AM

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Why don't they just join up with Micron, IBM, and Samsung and use Hybrid Memory Cube (HMC) It looks like they already have working prototypes. Here is one of many links around the web. http://www.engadget.com/2...micron-stack-their-chips/
0 0 [Posted by: yammerpickle2  | Date: 12/08/11 10:24:35 AM]
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