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Micron Technology and Xilinx this week demonstrated an FPGA interfacing with RLDRAM 3 [reduced latency DRAM] memory, a new and emerging memory standard for high-end networking applications such as packet buffering and inspection, linked lists, and lookup tables.

Operating with Virtex-7 and Kintex-7 FPGAs at data rates up to 1600MHz, Micron's high-performance RLDRAM 3 memory combines high density, high bandwidth and fast SRAM-like random access to enable a 60% percent higher data rate and memory bandwidth compared to that of the previous generation (Virtex-6 FPGAs/RLDRAM2 memory standard). RLDRAM 3 memory uses innovative circuit design to minimize the time between the beginning of an access cycle and the instant that the first data is available. Ultra-low bus turnaround time enables higher sustainable bandwidth with near-term balanced read-to-write ratios.

RLDRAM 3 memory will power 40G and 100G networking systems that require higher speed, higher density, lower power and lower latency. Virtex-7 and Kintex-7 FPGAs are designed with the necessary IO standards and architectural components for optimal interfacing with RLDRAM 3, providing a significant boost to system performance for high-performance wireless and wired networking systems.

"The new RLDRAM 3 interface is ideal for Xilinx and Micron's mutual customers in the high-end networking space who require higher speed, higher density, lower power and lower latency. The RLDRAM 3 hardware demonstration shows how we are able to achieve a much more efficient transfer of network data," said Derek Curd, technical marketing manager at Xilinx.

Xilinx RLDRAM 3 memory interface IP core is available now with user configurable IP cores available in ISE Design Suite 13.4 in September 2012. Qualified Micron RLDRAM 3 memory devices are available now in x18 and x36 organizations across all speed grades from 800 to 1066MHz.

Tags: Micron, Xilinx, RLDRAM

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