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JEDEC, a leading standard-setting organization, has announced the initial publication of its widely-anticipated DDR4 SDRAM standard. The new memory standard has been defined to provide higher performance, with improved reliability and reduced power, thereby representing a significant achievement relative to previous DRAM memory technologies.

“The publication of the JEDEC DDR4 standard represents the culmination of years of dedicated effort by memory device, system, component and module producers worldwide. The new standard will enable next generation systems to achieve greater performance, significantly increased packaging density and improved reliability - with lower power consumption,” said Joe Macri, chairman of JEDEC’s subcommittee for DRAM.

The per-pin data rate for DDR4 is specified as 1.6GT/s (giga transfers per second) to an initial maximum objective of 3.2GT/s. With DDR3 exceeding its original targeted performance of 1.6GT/s, it is likely that higher performance speed grades will be added in a future DDR4 update. Other DDR4 attributes tightly intertwined with the planned speed grades, enabling device functionality as well as application adoption, include: a pseudo open drain interface on the DQ bus, a geardown mode for 2,667MT/s per DQ and beyond, bank group architecture, internally generated VrefDQ and improved training modes.

The DDR4 architecture is an 8n prefetch with two or four selectable bank groups.  This design will permit the DDR4 memory devices to have separate activation, read, write or refresh operations underway in each unique bank group. This concept will also improve overall memory efficiency and bandwidth, especially when small memory granularities are used. More information about additional features may be found on the JEDEC website.

In addition, DDR4 has been designed in such a way that stacked memory devices may prove to be a key factor during the lifetime of the technology, with stacks of up to 8 memory devices presenting only a single signal load.

DDR4 offers a range of innovative features designed to enable high speed operation and broad applicability in a variety of applications including servers, laptops, desktop PCs and consumer products. The new technology has been defined with a goal of simplifying migration and enabling adoption of an industry-wide standard.

Tags: DDR4, DRAM, JEDEC, Samsung, Micron, Hynix


Comments currently: 5
Discussion started: 09/25/12 11:15:24 AM
Latest comment: 09/26/12 01:56:22 PM
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0 3 [Posted by: idonotknow  | Date: 09/25/12 01:49:38 PM]

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0 8 [Posted by: beenthere  | Date: 09/25/12 02:08:47 PM]
- collapse thread


My apu AMD hd-3850 feeds on RAM, so as alot of other people bought APU`s this year and previous, once AMD released an APU clocked to 800~900 mhz on the graphic side, plus DDR4 it will be like an AMD hd 7750 integrated on the cpu with 10~20% penalty cause using DDR4 instead of GDDR5
1 0 [Posted by: medo  | Date: 09/26/12 03:09:13 AM]
The future of PCs is moving towards integrated high performance graphics. The limiting factor lies squarely on the mainmemory bus speed.
0 0 [Posted by: KeyBoardG  | Date: 09/26/12 01:56:22 PM]


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