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Micron Technology, a leading supplier of dynamic random access memory (DRAM), said on Wednesday that it had initiated shipping 2GB hybrid memory cube (HMC) engineering samples. HMC represents a dramatic step forward in memory technology, and these engineering samples are the world's first HMC devices to be shared broadly with lead customers.

"System designers are looking for new memory system designs to support increased demand for bandwidth, density, and power efficiency. HMC represents the new standard in memory performance; it's the breakthrough our customers have been waiting for," said Brian Shirley, vice president of Micron's DRAM solutions group.

An industry breakthrough, HMC uses advanced through-silicon vias (TSVs) – vertical conduits that electrically connect a stack of individual chips – to combine high-performance logic with Micron's DRAM. Micron's HMC features a 2GB memory cube that is composed of a stack of four 4Gb DRAM die. The solution provides an unprecedented 160GB/s of memory bandwidth while using up to 70% less energy per bit than existing technologies, which dramatically lowers customers' total cost of ownership (TCO).

HMC's abstracted memory enables designers to devote more time to leveraging HMC's revolutionary features and performance and less time to navigating the multitude of memory parameters required to implement basic functions. It also manages error correction, resiliency, refresh, and other parameters exacerbated by memory process variation.

Micron expects 4GB HMC engineering samples to be available in early 2014 with volume production of both the 2GB and 4GB HMC devices beginning later in 2014.

HMC is designed for applications requiring high-bandwidth access to memory, including data packet processing, data packet buffering or storage, and computing applications such as processor accelerators. Micron expects future generations of HMC to migrate to consumer applications within three to five years.

"The Hybrid Memory Cube is a smart fix that breaks with the industry's past approaches and opens up new possibilities. Although DRAM internal bandwidth has been increasing exponentially, along with logic's thirst for data, current options offer limited processor-to-memory bandwidth and consume significant power. HMC is an exciting alternative," said Jim Handy, a memory analyst at Objective Analysis.

Tags: Micron, DDR3, DRAM, HMC


Comments currently: 5
Discussion started: 09/26/13 06:56:03 PM
Latest comment: 09/28/13 01:35:31 AM
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"Micron's HMC features a 2GB memory cube that is composed of a stack of four 4Gb DRAM die"

4*4=2 How does that work? Raided Memory?
0 0 [Posted by: KeyBoardG  | Date: 09/26/13 06:56:03 PM]
- collapse thread

4Gb *4 = 16Gb or 2GB.
It's bits for the chips and bytes for the module.
1 0 [Posted by: Christian Nicolaisen  | Date: 09/26/13 07:12:40 PM]

At 160GB/s this HMC already has the speed of 7ghz GDDR5. Let's see this with Excavator!
0 0 [Posted by: jesh462  | Date: 09/27/13 02:57:56 AM]
- collapse thread

Speed and bandwidth are very different. Just look at SSDs, they have bandwidth up to 550MB/s, but the latency is so high that 4kB packets can be 20x slower than sequential ones! It would be interesting to see the effects of latency on such a memory stacking method, could actually be lower than regular DDR3/4 simply by having less parts to deal with.
2 0 [Posted by: basroil  | Date: 09/27/13 08:02:08 AM]
Yeah, I remember reading/hearing that latency will also be improved compared with planar chips, but I have not seen any numbers going either way.

Add: Micron's HMC FAQ has this to say about latency: "Reduced Latency – With vastly more responders built into HMC, we expect lower queue delays and higher bank availability, which will provide a substantial system latency reduction—a key advantage in networking system design."
0 0 [Posted by: lol123  | Date: 09/28/13 01:35:31 AM]


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