One more technology has now been added to the "money box" of Yellowstone Project developed by Rambus Company (this is a faster signal memory interface announced in early autumn last year already). This technology is known as FlexPhase and is called to symbolize flexible data synchronization with the clock frequency inside the chip without involving any external clock circuits. This technology allows the memory makers to give up laying out the common synchronization circuits, which will simplify the design and manufacturing of the future DRAM. The synchronization error in this case lies within 2.5picoseconds.

This is already the third component of the so called Yellowstone technology. The other two are ODR (Octal Data rate) providing up to 8bit per clock data transfer rate and DRSL (Differential Rambus Signaling Levels). There have been already developed the first chip prototypes supporting these technologies (the prototype produced by TSMC with 0.13micron technology, which was showcased in Tokyo at the Rambus Developer Forum, Japan 2002.

The bandwidth of this prototype was around 3.2GB/sec, which is not that impressive actually (this is the same as by dual-channel PC800 RDRAM or single-channel DDR400/PC3200). However, the company claims that Yellowstone technology will allow reaching 3.2-6.4GHz frequencies and 10-100GB/sec memory bus bandwidth in the future.

The first systems using Yellowstone technology should be demonstrated in 2004. Well, hopefully Rambus will survive until then :)