Elpida Enables 1.60GHz DDR3 Memory with New Technologies
Elpida Develops New Circuit Technologies for DDR3 Memory
by Anton Shilov
02/12/2006 | 11:40 PM
Elpida Memory, a leading maker of memory, announced the development of new high-speed, low-power circuit technologies for high-speed DDR3 SDRAM in a paper presented at the International Solid State Circuits Conference (ISSCC). Using the new technologies, Elpida produced a 512Mb DDR3 device with a column access time of 8.75ns and clock-speed of 1.60GHz.
The new technologies consist of a transfer circuit that realizes high-speed access time (data readout time), and a data readout timing generator that enables stable high-speed data transfer rate in the dynamic random access memory’s (DRAM’s) output block.
Elpida found that the data readout speed could be increased by blanket-reading data from the DRAM’s memory array and transferring that data to the output circuit using time division, thus cutting down on the number of data signal lines required and reducing the parasitic capacitance. The company also devised a technology that would enable high-speed data transfer by developing counters that could control generation of the data readout timing on a clock with double the cycle time of DDR2 while still providing enough operating margin.
Elpida produced 512Mb DDR3 SDRAM devices using 90nm process technology. Repeated evaluation results showed that even at low 1.5V operation, consistent, high yield production of DDR3 SDRAM chips with low voltage-a column access time of 8.75ns and a data transfer rate of 1.6Gb/s is achievable using these new technologies. Elpida is ready to start the production of DDR3 SDRAM using these new technologies, the company indicated.
The new technologies developed by Elpida are the following:
- Time-division transfer of blanket-read data in the memory array: with the basic DDR3 system, eight bits of data are blanket read simultaneously from the DRAM’s memory array, enabling data to be read by the peripheral circuits eight times faster than the speed of data readout in the array. By executing at different times (time division) to split the transfer of data from the array to the output buffer circuit into two operations, the number of signal lines can be halved, enabling the expansion of the interval between the signal lines and reducing the parasitic capacitance. The result is a fast, noise-resistant data transfer circuit that can distribute a large concentration of current consumed during transfer. Confirming the sufficient performance of this circuit, test results showed a column access time of 8.75ns on an operating voltage of 1.5V in the DDR3 specification.
- Data readout timing generator operating on double input clock cycle: the start time of data is read from the memory array and must be controlled by counters that count the number of high peaks for the input clock signals and generate read activation signals at the specified clock count (CAS latency). However the DDR3 specification enables a DRAM input clock signal of up to 800MHz-double the speed of DDR2’s 400 MHz clock signal-requiring a counter circuit that supports this frequency. In other words, this has traditionally led to two major problems. The first is the difficulty of maintaining the operating time of this circuit once the input clock speeds up. The second is the inevitable increase in power consumption that occurs when most of the counters in the DRAM operate on a high-speed clock.
To solve these problems, Elpida has succeeded in developing a circuit technology that uses two types of counters: one type for when the designated clock count is even, and one for when it is odd. The specified clock count can be selected at certain times, such as when power is applied, from a range of clock counts defined in the DDR3 specification. The movement clock that controls the circuits divides the clock input to the DRAM to double the cycle. In other words, by operating half the counter circuits on a double-cycle clock, the counters’ operating time can be maintained and the current consumption is reduced to half the counter operation.
Tests results show that the circuit supports an input clock of 800MHz and achieves a transfer rate in the DRAM’s output block of 1.6Gb/s (or 1600MHz). Moreover, even when a high-speed clock was used, the standby current during clock operation showed a 22% drop.