JEDEC Discloses Key DDR4 Memory Peculiarities

JEDEC Unveils Key DDR4 Memory Attributes

by Anton Shilov
08/23/2011 | 12:08 PM

JEDEC on Tuesday announced selected key attributes of its widely-anticipated DDR4 standard. With publication forecasted for mid-2012, JEDEC DDR4 will represent a significant advancement in performance with reduced power usage as compared to previous generation technologies.

 

“Numerous memory device, system, component and module producers are collaborating to finalize the DDR4 standard, which will enable next generation systems to achieve greater performance with lower power consumption. JEDEC invites all interested companies worldwide to participate in the development of DDR4. The next committee meeting will be held in Chicago in September, 2011,” said Joe Macri, chairman of JEDEC’s JC-42.3 subcommittee for DRAM memories.

DDR4 is being developed with a range of innovative features designed to enable high speed operation and broad applicability in a variety of applications including servers, laptops, desktop PCs and consumer products. Its speed, voltage and architecture are all being defined with the goal of simplifying migration and facilitating adoption of the standard.

 

A DDR4 voltage roadmap has been proposed that will facilitate customer migration by holding VDDQ constant at 1.2V and allowing for a future reduction in the VDD supply voltage. Understanding that enhancements in technology will occur over time, DDR4 will help protect against technology obsolescence by keeping the I/O voltage stable.

The per-pin data rates, over time, will be 1.6 giga transfers per second (GT/s) to an initial maximum objective of 3.2GT/s. With DDR3 exceeding its expected peak of 1.6GT/s, it is likely that higher performance levels will be proposed for DDR4 in the future. Other performance features planned for inclusion in the standard are a pseudo open drain interface on the DQ bus, a geardown mode for 2667MHz data rates and beyond, bank group architecture, internally generated VrefDQ and improved training modes.

 The DDR4 architecture is an 8n prefetch with bank groups, including the use of two or four selectable bank groups. This will permit the DDR4 memory devices to have separate activation, read, write or refresh operations underway in each of the unique bank groups. This concept will improve overall memory efficiency and bandwidth, especially when small memory granularities are used.

 Additional features in development include:

To facilitate comprehension and adoption of the DDR4 standard, JEDEC is planning to host a DDR4 technical workshop following the publication of the standard. More information and details will be announced coincident with publication.