by Anton Shilov
12/16/2011 | 02:54 PM
Micron Technology, one of the largest DRAM companies in the world, this week said that it was working with JEDEC, an industrial standard setting organization, over standardization of a new DRAM interface and die-stacking technology called three-dimensional stacking, or 3DS. This technology may be a core tech behind DDR4.
The idea behind 3DS is to use specially designed and manufactured master-and-slave DRAM die, with only the master die interfacing with the external memory controller. 3DS technology uses optimized DRAM die, single DLL per stack, reduced active logic, single shared external I/O, improved timing, and reduced load to the external world. This combination of features can improve timing, bus speeds, and signal integrity while lowering both power consumption and system overhead for next-generation modules, according to Micron.
In its video demo, Micron shows a timing limitation when reading from one rank and then from another. Due to the system limitation, there is a one-cycle gap on the data bus, which impacts overall system bandwidth.
Micron’s 3DS devices offer the opportunity to eliminate this timing gap between read accesses from one rank to another. Our 3DS device can accept Read commands to different ranks so that the data bus is in constant use, claims Micron.
“In the second case, we are observing how data is continuous when the system issues consecutive Read commands on the same rank. A 3DS-optimized system will similarly take advantage of this tighter timing and be able to see improved data bus utilization and bandwidth when reading from different banks,” said Aftab Farooqi of Micron Technology.