by Anton Shilov
04/04/2012 | 09:46 PM
Originally, the DDR4 standard was supposed to be finalized in 2011 and the first production was expected to start in 2012. But after many redesigns and plan changes, the new memory standard will start to be used by Intel Corp. only in 2014 and starting from high-end servers, as the technology will provide the biggest benefits to multi-core/multi-socket machines.
Traditionally, Intel started to support new memory types by its client microprocessors for desktops and notebooks, where performance and low power consumption are key features. But with DDR4, which has a brand-new architecture and topology, Intel is projected to start supporting new type of memory with its Xeon EX/Haswell-EX multi-core/multi-socket platform in 2014, according to a VR-Zone report. Since Haswell-EX expandable platform for enterprise computing will feature microprocessors with 12-14 cores, it will not only benefit from lower power consumption by memory and high memory bandwidth, but also from extreme memory capacity that DDR3 simply cannot provide.
Intel's client chips in 2013 - 2014 timeframe - Haswell, Rockwell/Broadwell - will continue to rely on DDR3 memory since it is expected to provide enough bandwidth for mainstream applications with four cores and integrated graphics engine, especially with some tweaks like embedded DRAM, level four cache and so on.
Since Intel will leave DDR4 for its Skylake and Skymont generations of client chips in 2015 - 2016 period, DDR4 mass production will ramp sometimes in that timeframe. As a result, DDR3 memory will be the longest-lasting mainstream type of DRAM in the recent history of computing.
DDR4 is being developed with a range of innovative features designed to enable high speed operation and broad applicability in a variety of applications including servers, laptops, desktop PCs and consumer products. A DDR4 voltage roadmap has been proposed that will facilitate customer migration by holding VDDQ constant at 1.2V and allowing for a future reduction in the VDD supply voltage. The per-pin data rates, over time, will be 1.6 giga transfers per second (GT/s) to an initial maximum objective of 3.2GT/s. Other performance features planned for inclusion in the standard are a pseudo open drain interface on the DQ bus, a geardown mode for 2667MHz data rates and beyond, bank group architecture, internally generated VrefDQ and improved training modes.
The new levels of performance will require a tradeoff. In DDR4 memory sub-systems every memory channel will only support one memory module. As a result, to enable highest-possible memory capacities, DRAM makers will make high-capacity DDR4 chips using through-silicon-via (TSV) technology that will allow to increase capacity of memory chips at a very fast rate. For servers, special switches will be introduced to avoid one module/one channel limitation. As a result, server platforms will be able to accommodate much higher memory capacities than they can do now thanks to new levels of module capacities.