by Anton Shilov
08/15/2012 | 11:39 PM
The Hybrid Memory Cube (HMC) consortium this week said that its developer members have released the initial draft of the HMC interface specification to a rapidly growing number of industry adopters. The industry specification will enable adopters to fully develop designs that leverage HMC’s innovative technology, which has the potential to boost performance in a wide range of applications. HMC consortium (HMCC) hopes to release the final version by the end of this year.
The initial specification draft consists of an interface protocol and short-reach interconnection across physical layers (PHYs) targeted for high-performance networking, industrial, and test and measurement applications. The next step in development of the specification calls for the consortium’s adopters and developers to refine the specification and define an ultra short-reach PHY for applications requiring tightly coupled or close proximity memory support for FPGAs, ASICs and ASSPs.
“With the draft standard now available for final input and modification by adopter members, we are excited to move one step closer to enabling the Hybrid Memory Cube and the latest generation of 28nm FPGAs to be easily integrated into high-performance systems. The steady progress among the consortium’s member companies for defining a new standard bodes well for businesses who would like to achieve unprecedented system performance and bandwidth by incorporating the Hybrid Memory Cube into their product strategies,” said Rob Sturgill, architect, at Altera.
The interface specification reflects a focused collaboration among several of the world’s leading technology providers. Micron and Samsung, the initial developing members of the HMCC, are working closely with Altera, ARM, HP, IBM, Microsoft, Open-Silicon, SK Hynix and Xilinx to allow HMC to pave the way for a wide range of advances in electronics.
“The progress that’s been made on the HMC specification is extremely exciting to Xilinx because of the increasingly important role that our 28nm high-performance, low-power FPGAs are playing in high-performance systems,” said Hugh Durdan, vice president of portfolio and solutions marketing at Xilinx.
The Hybrid Memory Cube – which was jointly designed by Intel and Micron – demonstrates a new approach to memory design delivering a 7-fold improvement in energy-efficiency over today's DDR3. Hybrid Memory Cube uses a stacked memory chip configuration, forming a compact “cube”, and uses a new, highly efficient memory interface which sets the bar for energy consumed per bit transferred while supporting data rates of 1Tb/s (one trillion bits per second). This technology could lead to dramatic improvements in servers optimized for cloud computing as well as ultrabooks, televisions, tablets, smartphones and other low-power consumer electronics devices.
Adopter membership in the HMCC is available to any company interested in participating in development of the specification. The HMCC already has responded to interest from more than 115 prospective adopters. The final interface specification is scheduled for completion and release by the end of 2012.