by Anton Shilov
09/12/2012 | 05:14 PM
Samsung Electronics, the world's No. 1 maker of memory, has demonstrated its next-generation DDR4 chips and memory modules at Intel Developer Forum trade-show. The company has also disclosed its DDR4 roadmap for the next several years.
Setting the standard for DDR4 dynamic random access memory (DRAM) type has been going pretty slowly for many reasons. Originally, the DDR4 standard was supposed to be finalized in 2011 and the first production was expected to start in 2012. But after many redesigns and plan changes, the new memory standard will be finalized sometimes late this year and the new memory type will start to be used by Intel Corp. only in 2014.
During the trade-show, Samsung showcased already well-known high-density 16GB PC4-17000 (2133MHz) 284-pin DDR4 memory modules based on memory modules marked as K4A46045QB it unveiled earlier this year. This time, however, the modules carried switch/buffer chip from IDT, not Texas Instruments as before. The company also demonstrated a 300mm wafer with DDR4 dies processed using 30nm-class manufacturing technology, implying that it can start production of DDR4 anytime. Still, it will not as the standard itself is "only" 98% finalized.
But while the standard itself has not been set, it looks like Samsung's roadmap for DDR4 chips and modules is more or less ready. Next year the company plans to bump up speed of experimental high-density DDR4 modules to 2400MHz, whereas the first production chips/modules for servers due in 2014 will operate at 2666GHz effective frequency. Eventually, Samsung and Intel intend to boost the effective clock-speeds of DDR4 server memory modules to rather whopping 3.20GHz.
DDR4 is being developed with a range of innovative features designed to enable high speed operation and broad applicability in a variety of applications including servers, laptops, desktop PCs and consumer products. A DDR4 voltage roadmap has been proposed that will facilitate customer migration by holding VDDQ constant at 1.2V and allowing for a future reduction in the VDD supply voltage. The per-pin data rates, over time, will be 1.6 giga transfers per second (GT/s) to an initial maximum objective of 3.2GT/s. Other performance features planned for inclusion in the standard are a pseudo open drain interface on the DQ bus, a geardown mode for 2667MHz data rates and beyond, bank group architecture, internally generated VrefDQ and improved training modes.
The new levels of performance will require a tradeoff. In DDR4 memory sub-systems every memory channel will only support one memory module. As a result, to enable highest-possible memory capacities, DRAM makers will make high-capacity DDR4 chips using through-silicon-via (TSV) technology that will allow to increase capacity of memory chips at a very fast rate. For servers, special switches will be introduced to avoid one module/one channel limitation. As a result, server platforms will be able to accommodate much higher memory capacities than they can do now thanks to new levels of module capacities.
Anna Filatova, editor-in-chief at X-bit labs contributed, to this report.