Everspin Debuts First Spin-Torque MRAM for High Performance Storage Systems

Everspin Introduces First Spin-Torque MRAM with DDR3 Interface

by Anton Shilov
11/13/2012 | 08:11 AM

Everspin Technologies has begun to sell the world’s first spin-torque magnetoresistive RAM (ST-MRAM), a new type of high performance and ultra-low latency memory that is expected to transform storage architecture.

 

ST-MRAM is a performance-optimized storage class memory (SCM) that bridges the role of today’s conventional memory with the demands of tomorrow’s storage systems by providing non-volatility, high endurance and ultra-low latency. One example of potential use is in the area of cloud storage as more users and content are added, faster and consistent data storage access is a necessity.

“Our first ST-MRAM product has the potential to carry today’s high performance storage systems to greater heights. We are collaborating with select customers to allow them to evaluate and take advantage of Spin-Torque MRAM technology sooner and to gather feedback that will help us finalize our 64Mb DDR3 ST-MRAM for production,” said Phill LoPresti, president and CEO of Everspin Technologies.

Everspin’s proprietary spin-torque technology uses a spin-polarized current for switching. Data is stored as a magnetic state versus an electronic charge, providing a non-volatile memory bit that does not suffer wear-out or data retention issues associated with Flash technology. The EMD3D064M 64Mb ST- MRAM is functionally compatible with the industry standard JEDEC specification for the DDR3 interface, which delivers up to 1600MT/s, translating to memory bandwidth of up to 3.2GB/s at nanosecond class latency. The product is offered in an industry standard WBGA package aligned with the DDR3 standard.

The 64Mb device is the first product in Everspin’s ST-MRAM roadmap that is planned to scale to gigabit density memories with faster speeds. Select customers are now evaluating samples of Everspin’s EMD3D064M 64Mb DDR3 ST-MRAM.

“The properties of ST-MRAM are particularly appealing to the enterprise SSD market because of its ability to enhance and complement flash memory technology. The commercialization of this technology is an important industry milestone that should continue to drive SSD proliferation in data center and in-memory computing architectures,” said Joseph Unsworth, research vice president at Gartner.

ST-MRAM gives system designers the benefit of persistent, high endurance storage or memory for applications that demand better reliability and that need the performance boost of DDR3 speed. The 64Mb density MRAM provides an ideal entry point for non-volatile buffer and cache memory in solid state and RAID storage systems as well as storage appliances. The 64Mb device will complement existing low cost memory technologies, reducing overall system cost and complexity.

Everspin is manufacturing ST-MRAM on its 200mm production line in Chandler, Arizona and is collaborating with industry leaders to establish 300mm MRAM tools and additional fab capacity. Everspin is also working with design partners to ensure that the required tools and support are in place to drive the rapid adoption of ST-MRAM, including the necessary memory controllers, memory modules (DIMMs) and evaluation platforms.

Everspin is shipping working samples of the EMD3D064M 64Mb DDR3 ST- MRAM to select customers and will announce details on broad availability in 2013. In addition, Everspin is offering ST-MRAM non-volatile random access memory modules in industry standard configurations, and PCIe FPGA platforms are available now allowing customers to start designs.

"Existing memory technologies face significant challenges to deliver the right balance of performance, power consumption, and reliability as they scale to smaller process geometries. The commercialization of the first 64Mb Spin-Torque MRAM is an industry milestone along the path to broader use of more varied non-volatile memory technologies to improve storage device reliability, and to increase performance," said Jeff Janukowicz, research director for solid-state storage and enabling technologies at IDC.