Hybrid Memory Cube Consortium Publishes Final Specification of HMC Technology

Specifications of Hybrid Memory Cube Finalized

by Anton Shilov
04/03/2013 | 11:15 PM

More than 100 developer and adopter members of the hybrid memory cube consortium (HMCC) this week announced is has reached consensus for the global standard that will deliver a much-anticipated, disruptive memory computing solution. Developed in only 17 months, the final specification marks the turning point for designers in a wide range of segments to begin designing Hybrid Memory Cube (HMC) technology into future products.

 

"This milestone marks the tearing down of the memory wall. The industry agreement is going to help drive the fastest possible adoption of HMC technology, resulting in what we believe will be radical improvements to computing systems and, ultimately, consumer applications," said Robert Feurle, Micron's vice president for DRAM marketing.

Hybrid Memory Cube uses a stacked memory chip configuration, forming a compact “cube”, and uses a new, highly efficient memory interface which sets the bar for energy consumed per bit transferred while supporting extreme data rates.

The achieved specification provides an advanced, short-reach (SR) and ultra short-reach (USR) interconnection across physical layers (PHYs) for applications requiring tightly coupled or close-proximity memory support for FPGAs, ASICs and ASSPs, such as high-performance networking, and test and measurement. The next goal for the consortium is to further advance standards designed to increase data rate speeds from 10, 12.5 and 15Gb/s up to 28Gb/s for SR and from 10Gb/s up to 15Gb/s for USR. The next-generation specification is projected to gain consortium agreement by the first quarter of 2014.

The HMC standard focuses on alleviating an extremely challenging bandwidth bottleneck while optimizing the performance between processor and memory to drive high-bandwidth memory products scaled for a wide range of applications. The need for more efficient, high-bandwidth memory solutions has become particularly important for servers, high-performance computing, networking, cloud computing and consumer electronics. 

A major breakthrough with HMC is the long-awaited utilization of advanced technologies to combine high-performance logic with state-of-the-art DRAM. With this first HMC milestone reached so quickly, consortium members have elected to extend their collaborative effort to achieve agreement on the next generation of HMC interface standards. 

"The consensus we have among major memory companies and many others in the industry will contribute significantly to the launch of this promising technology. As a result of the work of the HMCC, IT system designers and manufacturers will be able to get new green memory solutions that outperform other memory options offered today," said Jim Elliott, vice president of memory planning and product marketing at Samsung Semiconductor.

The HMCC is a focused collaboration of OEMs, enablers and integrators who are cooperating to develop and implement an open interface standard for HMC. More than 100 leading technology companies from Asia, Japan, Europe and the U.S. have joined the effort, including Altera, ARM, Cray, Fujitsu, GlobalFoundries, HP, IBM, Marvell, Micron Technology, National Instruments, Open-Silicon, Samsung, SK Hynix, ST Microelectronics, Teradyne and Xilinx. Continued collaborations within the consortium could ultimately facilitate new uses in HPC, networking, energy, wireless communications, transportation, security and other semiconductor applications.