DDR4 Memory Standard Faces Updates Ahead of Commercialization

JEDEC Wants “Little More Tuning” of Next-Gen DRAM Standard

by Anton Shilov
01/03/2014 | 11:50 PM

Next-generation DDR4 memory standard is incoming. DDR4 memory modules will be used inside high-end desktops (HEDTs) based on Intel Core i7 “Haswell-E” chips as well as servers powered by Intel Xeon E5-2600 v3 “Haswell-EP” central processing units. But nothing is that rosy about the new memory standard. Apparently, the standard needs further tweaking.


“The initial DDR4 DRAM standard was targeted at early adopters, doubling the speed as well as improving performance scalability, capacity, and power efficiency in comparison to its predecessor,” said IHS iSuppli memory analyst Dee Robinson in an interview with EETimes web-site.

The per-pin data rate for DDR4 is specified as 1.6GT/s (giga transfers per second), an initial maximum data-rate plan of 3.2GT/s. With DDR3 exceeding its original targeted double data rate performance of 1.6GT/s, it is likely that higher performance speed grades will be added in into a DDR4 update. Other DDR4 attributes are reportedly tightly intertwined with the planned speed grades, enabling device functionality as well as application adoption, include: a pseudo open drain interface on the DQ bus, a geardown mode for 2,667MT/s per DQ and beyond, bank group architecture, internally generated VrefDQ and improved training modes.

"Going forward, the features are pretty much set, and we will do a little more fine-turning as well as add a few more speed bands. What ultimately decides whether there is a new specification rather than a revision is voltage supply and speed. If we are adding a feature, but not changing the voltage or the speed performance, then it will probably be an addendum to the spec,” said Scott Schaefer, a JEDEC committee member.

The DDR4 architecture features an 8n prefetch with two or four selectable bank groups. This design will permit the DDR4 memory devices to have separate activation, read, write or refresh operations underway in each unique bank group. This concept will also improve overall memory efficiency and bandwidth, especially when small memory granularities are used. More information about additional features may be found on the JEDEC website.

In addition, DDR4 has been designed in such a way that stacked memory devices may prove to be a key factor during the lifetime of the technology, with stacks of up to 8 memory devices presenting only a single signal load. This approach has a drawback as well: only one memory module per DDR4 channel is supported. Limitations of DDR4 will not resolved until DDR5, which is years away.

“Changes to the form factor in support of better speeds or lowering voltage is seen as a new technology. In order to make the jump to DDR5, it would require major new features, a lower power supply and changes to the form factor,” said Mr. Schaefer.

Samsung Electronics and SK Hynix, two major DRAM makers, have been shipping DDR4 memory samples since 2011.

Boostments to DDR4 standard will unlikely have a significant effort to its availability on the mass market since adoption of the technology by mainstream personal computers will only happen sometimes in 2015.