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Just three years ago only enterprise-class servers or very high-end workstations had four processing engines and it was nearly impossible to imagine this kind of performance in a mobile workstation. But it will be a reality in a less than a year from now, when Intel releases its quad-core central processing unit (CPU) that it received from the fab just days ago and already demonstrated at an even in Taiwan.

At the Intel Developer Forum (IDF) in Taiwan Intel demonstrated its first notebook processor for notebooks up and running, reports DigiTimes web-site. The chip, according to Shmuel “Mooly” Eden, Intel’s vice president and general manager of mobile platforms group, was received from an Intel’s fab just days ago, but it is fully functional, which is not really surprising, as it is based on the code-named Penryn micro-architecture that is due to become commercially available in less than a month from now.

The first quad-core mobile processors will feature 12MB of cache, use 1066MHz processor system bus (PSB), have thermal envelope of 45W and will be made using 45nm process technology. The chips will be marketed as Intel Core 2 Extreme CPUs and will aim mostly high-performance notebooks for content creating and gaming.

Intel’s first quad-core processors for mobile computers will be a part of the code-named Montevina platform and will hardly be drop-in compatible with current Santa Rosa, or its refresh, platforms.

Intel did not comment on the news-story.

Intel announced in March that the new “Penryn” family chips produced using 45nm process technology will have greater instructions per clock (IPC) execution, which means that they will be faster and more efficient even at the same clock-speeds with the current generation chips. Besides, the new chips will be able to run at higher clock-speeds compared to today’s Core 2 Duo and Core 2 Quad products.

The major micro-architectural improvements for new Intel Core 2 processors, besides SSE4 instruction set, include the so-called Unique Super Shuffle Engine and Radix 16 technique. The Super Shuffle Engine is a full-width, single-pass shuffle unit that is 128-bits wide, which can perform full-width shuffles in a single cycle. This significantly improves performance for SSE2, SSE3 and SSE4 instructions that have shuffle-like operations such as pack, unpack and wider packed shifts. This feature will increase performance for content creation, imaging, video and high-performance computing. Radix 16 technique, according to Intel, roughly doubles the divider speed over previous generations for computations used in nearly all applications. In addition, Intel also improved virtualization technology as well as added some features to dynamic acceleration technology, which is supposed to boost single-threaded applications’ performance on multi-core chips.


Comments currently: 5
Discussion started: 10/18/07 02:43:57 PM
Latest comment: 12/27/07 06:47:30 PM


Is it just me, or is this the only site where its referred to as a PSB instead of a FSB.
0 0 [Posted by:  | Date: 10/18/07 02:43:57 PM]


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