by Anton Shilov
05/18/2005 | 04:51 AM
UPDATE: Removing possibly sensible comments that contain business-related information that is not to be disclosed.
VIA Technologies on Wednesday retracted an earlier claim of its representative who said the company’s future processors would be compatible with Intel’s Pentium M platform infrastructure. The company said while the chips will have 479-pin packaging, they would not use Intel’s AGTL+ Quad Pumped Bus.
“VIA is developing a new VIA C7 processor, which will be based on the V4 bus architecture. We can confirm that the new chip will be manufactured using 90nm IBM SOI process. Further technical details will be released at the later time,” said Michal Lisiecki, a spokesman for VIA Technologies.
Late on Monday a claim that a future VIA processor would be pin-to-pin compatible with Intel Pentium M and Celeron M chips was published at a web-site, which also reported that at least one tier-one Taiwanese mainboard manufacturer was already working on a product to support such a chip. On Tuesday a
According to a VIA official in
VIA’s C7-M processors, also known as Esther (also code-named C5J, Cyrix 4), incorporate 128KB L1 cache and 256KB of L2 cache, a 800MHz processor system bus as well as SSE, SSE and SSE3 multimedia instructions. The chips are anticipated to run at speeds of around 2GHz eventually, VIA indicated last year. The C7-M core extends the VIA PadLock Hardware Security Suite to include execution (NX bit) protection, Montgomery Multiplier support for RSA encryption and secure Hash (SHA-1 and SHA-256) algorithms in addition to the VIA PadLock RNG and VIA PadLock ACE that are featured in the current VIA C5P Nehemiah processors.
The official announcement and finalized details on the matter of the VIA C7-M and supporting platforms are expected to be released at VIA Technology Forum 2005 which will be held in Taiwan, Taipei, at the same time as Computex Taipei 2005 trade-show: from the 31st of May to the 4th of June, 2005.