by Anton Shilov
08/17/2005 | 08:31 PM
VIA Technologies unveiled its new VIA VN800 core-logic that can support both VIA’s and Intel’s processors. The new chipset is primarily aimed at manufacturers of low-power and low-cost notebooks and is designed to provide additional flexibility for them when choosing a processor, but in order to achieve this VIA needs to have a C7-M chip pin-to-pin compatible with Intel’s mobile processors.
The new VIA VN800 chipset supports processors with VIA V4 or Intel AGTL+ processor system bus at the speed of 400MHz, 533MHz and 800MHz. The core-logic features single-channel DDR/DDR2 memory controller that supports up to PC3200 and PC2-4200 standards. The VN800 sports built-in S3 Graphics UniChrome Pro IGP graphics core as well as AGP 8x port for external graphics chips. The novelty from VIA sports V-Link bus to connect the VT8237A I/O hub providing PCI, USB, Parallel ATA, Serial ATA-150 and other controllers.
The VIA VN800 is optimized for ultra low power consumption to maximize battery life with advanced ACPI support that powers down certain functions of the chipset when not in use. Further, when paired with the VIA C7-M processor, the VIA VN800 offers support for VIA PowerSaver, which can reduce power consumption by as much as 50% by dynamically adjusting processor states, according to the developer.
VIA said that thanks to its own Flexi-Bus technology the VN800 provides notebook manufacturers “maximum design flexibility” by supporting VIA C7-M, Intel Pentium M and Intel Pentium 4 processors with Hyper-Threading technology. However, in order to be drop-in compatible with mainboards based on the VIA VN800 designed for both Intel and VIA microprocessors, the C7-M will need to feature packaging similar to that used by Intel. Initially the C7-M chips are available only in nanoBGA packaging, whereas Intel Pentium M and Intel Pentium 4 come in mPGA478 or mPGA479 form-factors. Earlier this year VIA said that the C7-M chips will also exist in 479-pin packaging.
VIA’s C7-M processors, also known as Esther (also code-named C5J, Cyrix 4), incorporate 128KB L1 cache and 256KB of L2 cache, a 800MHz processor system bus as well as SSE, SSE and SSE3 multimedia instructions. The chips are anticipated to run at speeds of around 2GHz eventually, VIA indicated last year. The C7-M core extends the VIA PadLock Hardware Security Suite to include execution (NX bit) protection, Montgomery Multiplier support for RSA encryption and secure Hash (SHA-1 and SHA-256) algorithms in addition to the VIA PadLock RNG and VIA PadLock ACE that are featured in the current VIA C5P Nehemiah processors.