by Anton Shilov
01/02/2013 | 08:54 PM
It is not a secret that Advanced Micro Devices intends to showcase the first accelerated processing units (APUs) based on its new low-power Jaguar x86 general-purpose cores behind closed-doors at the Consumer Electronics Show later this month. Apparently, AMD also intends to speed up the official debut of the new APUs and introduce them this calendar quarter.
AMD’s Kabini and Temash APUs will feature up to four x86 cores based on Jaguar micro-architecture, new-generation DirectX 11.1-compliant graphics adapter as well as a number of improvements related to heterogeneous processing and system architecture. Even though earlier it was expected that Kabini and Temash would feature integrated input/output capabilities in addition to a new memory controller, which would greatly simplify designs of netbooks, ultra-thin notebooks and other low-power devices. However, NotebookItalia web-site reports that both new APUs will rely on code-named Yangtze I/O controller.
In a bid to improve its positions on the market of netbooks, low-cost thin notebooks, tablets and other mobile devices, AMD will introduce Kabini (low-cost PCs) and Temash (media tablets and netbook convertibles) already in the first quarter of 2013, in March. It is logical to expect the launch at CeBIT 2013 since AMD typically makes big announcements at the trade-show.
Thanks to new-generation Jaguar x86 micro-architecture, which allows to boost clock-speed compared to currently-available Bobcat micro-architecture by 10% without increase of power consumption and 15% higher efficiency of the new cores versus predecessors, it is logical to expect Kabini APUs to provide decent performance increase compared to both current-gen low-power APUs from AMD as well as outdated Atom chips from Intel Corp.
In order to significantly improve performance of Jaguar-based APUs over the Bobcat-powered chips, AMD decided to go into virtually all logical directions: increase the amount of cores, boost clock-speed, add support for modern instructions, increase amount of executed instructions per clock (IPC). AMD also decided to improve power efficiency through clock gating and unit redesign in a bid to ensure lower idle power consumption compared to existing low-power designs. Jaguar features SSE4.1, SSE4.2, AES, PCLMUL, AVX, BMI, F16C as well as MOVBE. Jaguar also introduces 128-bit floating point unit (FPU) with enhancements and double-pumping to support 256-bit AVX instructions as well as an innovative integer unit with new hardware divider, larger schedulers and more out-of-order resources. AMD implemented a new CC6 state with even deeper energy economy, with each core able to go there independently.