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IBM and Vivendi Universal Games along with High Moon Studios and Radical Entertainment will host a session for Vivendi’s game developers in order to educate them on creation of games for the PlayStation 3 game console and more efficiently use the Cell processor.

“The Cell Broadband Engine is complex high-performance architecture that processes millions of pieces of information per second to deliver highly detailed graphics. Our focus is also on enabling the broader eco-system of game developers to fully utilize the power of the Cell Broadband Engine,” said Hal Lasky, vice president of consumer, media and entertainment for IBM global engineering solutions in a statement.

It is remarkable that neither Sony Computer Entertainment Inc., nor IBM, provided comprehensive training for game devs before the Sony PlayStation 3 game console was launched. It has been widely acknowledged that development of applications for the Cell processor is not a trivial task and game developers will need additional time to learn how to use the Cell BE more efficiently.

“[It] would have been great to get it before launch, but the information wasn’t available at the time, so they are seeking it out now,” Clinton Keith, chief technology officer for High Moon, said, reports DevX web-site.

Mr. Keith said that even Resistance: Fall of Man game title, which is currently considered as the most visually appealing game for the PS3, does not use the potential of the Cell processor.

“There will be titles in 3-4 years from now which will shock you,” Mr. Keith said.

Nevertheless, neither SCEI or IBM are going to host “brainstorm sessions” for Vivendi or other game developers. Norman Liang, business development manager for IBM global engineering solutions, said this brainstorm session is an extra initiative done at Vivendi’s behest, not IBM’s, and if competitors like Electronic Arts and Take 2 Interactive want to hold a similar event, they are welcome to do so.

The Cell microprocessor, which was jointly developed by IBM, Sony and Toshiba, incorporates one dual-threaded PowerPC core and eight so-called synergistic processing engines (SPEs) intended for floating-point calculations, the most demanding tasks in entertainment, workstation and server systems. The PowerPC core is projected to have 32KB L1 cache and 512KB L2 cache, while each of the SPEs will have 256KB of cache. The Cell has built-in Rambus XDR memory interface, capable of data rates from 3.20GHz to 8.0GHz. The chip also uses FlexIO processor buses that are capable of running at up to 6.40GHz.


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