Everybody know that TSMC and its clients still have some problems with developing and manufacturing complex and not so complex chips using 0.13 micron fabrication technology. There is no surprise that the company constantly postpones the commercial launch of its 90nm manufacturing technology as well. EEDesign reports that Taiwan Semiconductor Manufacturing Company will shortly introduce a new set of guidelines for chip design using such tiny technologies.

According to the report, TSMC’s Reference Flow 4.0 should help mitigate physical-design problems early on so that designers can spend less time troubleshooting later. Though it is not the first set of design rules to come out of TSMC, its scope goes far beyond earlier versions and brings into the mainstream certain design techniques once considered the realm of specialists.

TSMC claims that its Reference Flow 4.0 is the industry’s first complete design flow that responds specifically to 130 and 90nm design challenges and features dual physical implementation tracks built around commercial EDA tools primarily from Synopsys and Cadence Design Systems. Reference Flow 4.0 provides IC design teams with the flexibility to tap into TSMC’s recommended design methodologies independent of tool preferences, while directly addressing technical challenges related to designing at 0.13 micron and 90nm.

The new design rules should not only help small startups to develop their new chips using leading fabrication technologies on time, but also to allow big fabless semiconductor companies to manufacture faster chips with complex designs. At least, we may expect companies like ATI Technologies and NVIDIA to take advantage from the new guidelines sometime in future.