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Rambus announced earlier this week it has provided its customers with first samples of chips supporting the PCI Express interface. Rambus customers are using this chip to evaluate the RaSer physical layer (PHY) cell for PCI Express applications. The new chip can be combined with FPGAs, ASICs or other chips on PCI Express boards to be used for compliance and interoperability testing.

Rambus’ PCI Express PHY evaluation chip is the first to be implemented on a TSMC 0.13 micron process and has been delivered to customers for system level testing. The chip supports four PCI Express lanes, to address x4, x8, x16 and x32-lane based PCI Express devices used in chipset, graphics, and switch-based applications for PCs, servers and communications systems. The chip meets PCI Express specifications, including the jitter requirements, and supports key functions such as Receiver Detect and Beacon Generate and Detect features.

The RaSer PCI Express PHY features low power consumption - 80mW power per lane - and a small die area. The RaSer PHY is based on a proven SerDes cell used in InfiniBand and Ethernet XAUI products. Rambus offers a configurable Physical Coding Sublayer (PCS) layer to provide customers a flexible interface to the PCI Express MAC and upper logic layers.

Rambus’ PCI Express PHY may eventually be used in various types of applications, including, but not limited to, personal computers, servers, communication appliances and so on.


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