At the VLSI Symposium in
One set of transistors presented today use fully-depleted Silicon-on-Insulator (FDSOI) technology and deliver the highest PMOS (P-channel metal-oxide semiconductor) transistor speed ever published: up to a 30% increase versus previously published transistors. The other set use Strained-Silicon and AMD metal gate technology to deliver 20-25% higher NMOS (N-channel metal-oxide semiconductor) performance relative to conventional Strained-Silicon transistors.
AMD's latest transistors utilize a new form of transistor gate technology pioneered by AMD. Rather than using Polysilicon, the gate material used in most transistors today, AMD researchers used a material called Nickel Silicide to make "metal gates" within the transistors. Transistor gates turn the flow of electrical current through the transistor on and off and are a key element of a transistor's structure.
AMD used a combination of its metal gates and FDSOI to create a PMOS transistor with significantly improved gate conductance, appropriately engineered workfunction and enhanced carrier mobility. The combination of these effects resulted in transistor speed up to 30 percent higher than any previously published PMOS data at the time of testing. Performance ratings are based on the industry standard benchmark used for calculating transistor switching speed.
AMD's combination of its metal gates with Strained-Silicon in an NMOS (N-Channel Metal Oxide Semiconductor) transistor demonstrated similarly positive effects on gate conductance, workfunction, and carrier mobility, in addition to the mobility enhancement resulting from the Strained-Silicon layer. A transistor performance increase of 20-25% was achieved over conventional Strained-Silicon devices at the time of testing.
FDSOI and Strained-Silicon Details
Currently, SOI transistors are built on a thin top-layer of pure Silicon that sits atop another layer of insulating oxide. The insulating layer ensures that electrical current flows only through the thin top-layer of Silicon, and doesn't leak down into the material that forms the bulk of the wafer.
The thinness of the Silicon top-layer contributes to better transistor performance, in part because it minimizes undesirable electrical characteristics that could inhibit transistor operating efficiencies. Fully depleted SOI, an advance over today's SOI technologies, could offer higher performance capabilities thanks to a much thinner top-layer of Silicon.
Strained-Silicon transistors offer increased performance potential due to the Silicon atoms being “strained” to enhance carrier mobility, which results in improved electrical current flow. Emerging research shows that SOI and Strained-Silicon can be integrated within the same fabrication process to achieve additive benefits.