Intel Corporation showcased today its first working silicon made using 65nm technology process that will reach the commercial production stage in 2005. The company describes the new process as a process with high-performance low-power transistors – the main goal of every new fabrication technology.

“This accomplishment puts Intel's 65 nm technology on a fast track to extend our 15 year record of ramping production on a new process generation every two years. In fact, only 20 months have elapsed since we disclosed achievement of fully functional SRAMs on our 90nm process, which is now ramping,” said Dr. Sunlin Chou, senior vice president and general manager of Intel's Technology and Manufacturing Group.

The paramount details of the new process are Intel’s new advanced transistors, strained silicon technology and copper interconnects with new low-k dielectric:

• Intel’s new 65nm process will feature transistors measuring only 35nm in gate length, which will be the smallest and highest performing CMOS transistors in high-volume production. By comparison, the most advanced transistors in production today, found in Intel Pentium 4 "Prescott" processors, measure 50nm. Small, fast transistors are the building blocks for very fast processors.
• Intel has integrated the second-generation version of its strained silicon into this process. Strained silicon provides higher drive current, increasing the speed of the transistors with only a 2% increase in manufacturing cost.
• The process integrates eight copper interconnect layers and uses a “low-k” dielectric material that increases the signal speed inside the chip and reduces chip power consumption.

“The 65 nm process will enable us to make better products at lower cost, as we continue to innovate and extend Moore's Law,” Chou added.

Intel has used its 65nm process to make fully functional, 4Mb SRAM chips with a very small 0.57 square micron cell size. Small SRAM cells allow for the integration of larger caches in microprocessors. The SRAM cells have robust operating characteristics, with a solid noise margin indicating very efficient on/off switching properties. Each SRAM memory cell has six transistors: 10 million of these transistors would fit in one square millimeter.

The 65nm semiconductor devices were manufactured at Intel’s 300 mm development fab (called D1D) in Hillsboro, Oregon, where the process was developed. D1D is Intel’s newest fab and contains its largest individual clean-room measuring 176 000 square feet, which is roughly the size of three and a half football fields.

Intel’s in-house mask making team has been critical in building advanced masks that extend the existing 193 nm wavelength lithography equipment for use with the 65nm process generation. The company expects to reuse the 193nm and 248nm lithography equipment currently used on its 90nm process, as well as adding some upgraded 193nm tools. This lowers implementation costs and ensures a mature tool set for the manufacturing ramp. The 65nm process is on track to be ramped into high volume in D1D and transferred to other 300mm manufacturing fabs starting in 2005.