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HyperTransport Technology Consortium, an industrial organization that develops chip-to-chip interconnection technologies, today unveiled new specifications for the second version of the HyperTransport technology that is successfully deployed in numerous applications.

The HyperTransport Release 2.0 Specification introduces three more powerful bus speeds and maps to PCI Express, the successor of PCI for the next decade. HyperTransport’s speed capability extends from current 1.6Gb/s per pin to 2.0Gb/s, 2.4Gb/s, and 2.8Gb/s per pin using dual-data rate clocks at 1.0GHz, 1.2GHz, and 1.4GHz, delivering a maximum aggregate bandwidth of 22.40GB/s from current 12.8GB/s in both directions.

“Release 2.0’s substantial speed and bandwidth extensions combined with PCI Express bus extensibility reaffirm and consolidate HyperTransport’s long term chip-to-chip I/O technology leadership while preserving HyperTransport’s low implementation cost and the multi-million dollars investments made by the HyperTransport Consortium members and their considerable customer base,” a spokesperson for the HyperTransport Technology Consortium said.

The electrical protocols supporting the new clock rates are backward compatible with all previous versions of the HyperTransport electrical specifications. Moreover, parts compatible with PCI Express will also be compatible with the new HyperTransport 2.0.

HyperTransport technology was developed by a group of companies headed by CPU maker Advanced Micro Devices. No surprise that AMD is actually one of the most interested companies in development of the transfer protocol. Reportedly, AMD will introduce its new Athlon 64 processors with 1GHz HyperTransport bus in the late first quarter of the year.

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