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Rambus unveiled its Turbo PCI Express physical layer (PHY) platform which supports data rates of 5.0-6.4GHz, as well as the 2.5GHz data rate for today’s PCI Express applications. This dual-mode capability allows system developers to increase bandwidth without re-architecting their current PCI Express-compliant system designs.

The Turbo PCI Express platform includes a full-featured, drop-in physical layer (PHY) cell based on Rambus’s silicon-proven RaSer serial link technology and offers chip customers a two times increase in bandwidth over current PCI Express interface designs.

Rambus will provide an overview of the implementation challenges addressed by the Turbo PCI Express PHY and demonstrate the platform at the Rambus Developer Forum (RDF) early next month in Tokyo, Japan.

"Rambus was the first to demonstrate a 5.0-6.4Gbps backplane serial link platform and we have since developed a suite of PCI Express PHY products, helping to enable the industry's adoption of the PCI Express standard,” said Kevin Donnelly, vice president of the Logic Interface Division at Rambus.

“We have implemented PCI Express PHYs in more than four processes and continue to work actively with logic partners to ensure full interoperability with the upper protocol layers of the PCI Express standard. Our engineers have analyzed the technical challenges associated with increasing the speed of PCI Express and are ready to support early adopter customers who are planning for their next-generation solutions,” Mr. Donnelly added.

The new Turbo PCI Express PHY uses many of Rambus’ patented serial link technologies and innovations to support existing PCI Express clock sources, connectors, and board designs, while being able to auto-negotiate between 2.5GHz and higher rates, such as 5.0GHz data rates. Rambus’ Turbo PCI Express PHY platform will serve as a basis for a PCI Express second generation PHY product, when such specifications are finalized and become publicly available.

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