Intel Corp. Monday said it had achieved a yet another breakthrough in fabrication processes by manufacturing the world’s first 70Mb SRAM chip using 65nm technology. The new manufacturing process is expected to go online next year and to deliver a number of peculiarities to reduce current leakage processes and thus decrease power consumed by chips.
Moore’s Law, the Saga Continues
The company has built fully functional 70-megabit static random access memory (SRAM) chips with more than half a billion transistors using the world's most advanced 65nm process technology. The achievement extends Intel’s effort to drive the development of new manufacturing process technology every two years, in accordance with
The transistors in the new 65nm technology have gates measuring 35nm, approximately 30% smaller than the gate lengths on the previous 90nm technology. For comparison, about 100 of these gates could fit inside the diameter of a human red blood cell.
The new process technology increases the number of tiny transistors squeezed onto a single chip, giving Intel the foundation on which to deliver future multi-core processors, and to design innovative features into future products, including virtualization and security capabilities. Intel’s new 65nm process technology also includes several unique power-saving and performance-enhancing features.
Intel's 65nm semiconductor devices were manufactured at the company’s 300mm development fab (called D1D) in
65nm to Reduce Power Consumption
Intel’s strained silicon technology, first implemented in its 90nm process technology, is further enhanced in the 65nm technology. The second generation of Intel strained silicon increases transistor performance by 10 to 15% without increasing leakage. Conversely, these transistors can cut leakage by four times at constant performance compared to 90nm transistors. As a result, the transistors on Intel’s 65nm process have improved performance without significant increase in leakage.
Intel’s 65nm transistors have a reduced gate length of 35nm and a gate oxide thickness of 1.2nm, which combine to provide improved performance and reduced gate capacitance. The reduced gate capacitance ultimately lowers a chip’s active power. The new process also integrates eight copper interconnect layers and uses a “low-k” dielectric material that increases the signal speed inside the chip and reduces chip power consumption.
Intel has also implemented “sleep transistors” in its 65nm SRAM. Sleep transistors shut off the current flow to large blocks of the SRAM when they are not being utilized, which eliminates a significant source of power consumption on a chip. This feature is especially beneficial for battery-powered devices, like laptops.