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AMD and IBM Monday said they had jointly developed a new and unique strained silicon transistor technology aimed at improving processor performance and power efficiency. The new process increase transistor speed and will be incorporated into AMD’s future single-core and multi-core chips as well as into IBM’s Power processors.

The process named Dual Stress Liner reportedly results in up to a 24% transistor speed increase, at the same power levels, compared to similar transistors produced without the technology. The innovative strained silicon process enhances the performance of both types of semiconductor transistors, called n-channel and p-channel transistors, by stretching silicon atoms in one transistor and compressing them in the other. The dual stress liner technique works without the introduction of challenging, costly new production techniques, allowing for its rapid integration into volume manufacturing using standard tools and materials, according to AMD-IBM statement.

Faster, more power-efficient transistors are the building blocks of higher performance, lower power processors. As transistors get smaller, they operate faster, but also risk operating at higher power and heat levels due to electrical leakage or inefficient switching. AMD and IBM’s jointly developed strained silicon helps overcome these challenges. In addition, this process makes AMD and IBM the first companies to introduce strained silicon that works with silicon-on-insulator (SOI) technology, resulting in an additive performance and power savings benefit.

AMD intends to gradually integrate the new strained silicon technology into all of its 90nm processor platforms, including its future multi-core AMD64 processors. AMD plans to ship the first 90nm AMD64 processors using the technology in the first half of 2005.

IBM plans to introduce the technology on multiple 90nm processor platforms, including its Power Architecture-based chips, with the first products slated to begin shipping in the first half of 2005.

Details of the AMD-IBM Dual Stress Liner innovation will be disclosed at the 2004 IEEE International Electron Devices Meeting in San Francisco, Calif. from December 13 - 15, 2004. The Dual Stress Liner with SOI technology was developed by engineers from IBM, AMD, Sony and Toshiba at IBM’s Semiconductor Research and Development Center (SRDC) in East Fishkill, NY, as well as engineers from AMD at its Fab 30 facility in Dresden, Germany.

IBM and AMD have been collaborating on the development of next-generation semiconductor manufacturing technologies since January 2003.

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