The PCI-SIG, the Special Interest Group responsible for PCI Express architecture, announced that the data rate for the next planned revision of the PCI Express specification will be 5GHz, which is two times higher compared to today’s 2.50GHz speed. The new spec will be finalized in the second half of 2005 with actual products shipping in 2007.
The PCI-SIG board of directors considered market requirements and technical analysis of a range of data rates to obtain the most feasible, highest performance, backward compatible solution within the current PCI Express ecosystem, the company’s statement said. Platform implementation cost, high-volume manufacturability, system topologies, validation and interoperability were the key considerations studied by the PCI-SIG board members in the process to extend the PCI Express data rate to 5GT/s (billions of transfers per second).
“The new 5GT/s PCI Express specification will enable the required performance boost for bandwidth-hungry applications such as cinema-quality graphics and multimedia, enterprise servers and storage, and multi-gigabit networking,” said Ajay Bhatt, chairman of the PCI Express steering committee, responsible for managing the technical development and coordination of PCI Express specifications.
This new specification extends the performance capability of its flagship I/O interconnect architecture to meet the anticipated system requirements across computer and communication industry applications. The doubling of the data rate follows historical performance increases for I/O specifications in the industry. Many of the leading electrical experts who developed the PCI Express 1.0a specifications have been chartered to draft the new specification. The PCI-SIG expects to deliver the new specification in the second half of 2005 in time for product introductions beginning in 2007.
PCI-SIG reassured that the new PCI Express 5GHz systems will be backwards compatible with existing PCI Express 2.5GHz hardware. However, it is unclear, whether future products are able to function on current PCI Express implementation.