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Taiwan Semiconductor Manufacturing Company said Wednesday its Nexsys 90nm process continued a volume production ramp that would accelerate dramatically throughout 2005. The company said it initiated commercial products shipments to Altera, Qualcomm and some other and more of its clients likely to use the process next year.

Thousands of 90nm 300mm Wafers Shipping to Clients

TSMC began 90nm volume production in the third quarter of 2004 following the successful delivery of numerous customer chips in first-pass silicon. The company anticipates that near 40 single-product mask sets will tape out in 2004 and that 30 more products will tape out on mask-sharing Cybershuttle wafers before year’s end. Among these products, close to ten have entered production stage and many others are either in qualification or design verification.

“TSMC expects that 90nm demand will increase at a rapid pace in 2005, across a range of applications in consumer, communications, PC and industrial markets. To support this strong demand, TSMC is preparing a major capacity expansion, and an aggressive ramp of 90nm technology in Fab 12 and Fab 14 during 2005,” said Dr. Genda Hu, vice president of marketing for TSMC.

TSMC’s Nexsys 90nm technology is currently running in TSMC Fab 12 Phase I and will also be deployed in TSMC Fab 12 Phase II and TSMC Fab 14 as those 300mm production facilities ramp to production. The company states that it has reached several thousand 300mm wafers per month production level using Nexsys 90nm technology in the fourth quarter of 2004 and will ramp to higher volumes throughout 2005.

TSMC’s key-customer ATI Technologies recently accused insufficient output of TSMC’s 0.13 micron low-k products in its failure to deliver certain products in enough quantity. ATI’s next-generation graphics processor called R520 has been taped out using 90nm process technology at TSMC already.

90nm Brings Higher Speeds, Lower Costs

“Our customers are designing to the 90nm Nexsys technology for a variety of reasons, including higher density and smaller chip size, faster performance, battery-saving lower power consumption, and lower die cost that is further enhanced by our 300mm production. The Nexsys 90nm process has matured with very competitive defect density and process control. The TSMC DFM (Design for Manufacturing) offerings can help customers to reduce the time to volume production,” Dr. Hu said.

The Nexsys 90nm process provides a 2-times gate density improvement, 35% faster speed, 60% improvement in active power savings and a 20% interconnect RC improvement versus TSMC’s 130nm process, based on a general-purpose ring oscillator, according to the company.

TSMC’s Nexsys 90nm process is a full system-on-chip platform providing both CMOS logic and mixed-signal options with embedded high-density memories including 1TRAM 6TRAM, and 8TRAM. In addition, the new technology features multiple transistor types for improved power/speed/leakage tradeoffs.

The Nexsys 90nm logic family includes the high-volume general purpose (G) process as well as low power (LP) and high-speed (GT) options. Each supports multiple Vt options including low, standard, and high. Operating voltage is 1-1.2V; the I/O voltages range from 1.8 to 3.3V, depending on family member. SRAM memory densities range from 1.65-micron2 to 0.99-micron2.

TSMC’s Nexsys process is supported by the industry’s most extensive portfolio of validated, process-proven libraries, including standard cells, SRAM, I/O and specialty libraries. The Nexsys process is also backed by TSMC Reference Flow 5.0, the industry’s first reference flow providing critical power closure and integrated chip-to-package design for nanometer system-on-chip (SoC) integrated circuits.


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