X-bit labs

Freescale, Soitec Test 45nm Process Technology.

Category: Other

by Anton Shilov

[ 04/26/2005 | 03:11 AM ]

Freescale Semiconductor and Soitec Group recently demonstrated results in their collaborative effort in development of the sub-65nm nodes by producing the world’s first 45nm CMOS devices on bonded strained SOI substrates.

Company officials report that they launched the collaborative effort two years ago to evaluate strained SOI as the potential base material for sub-65-nm devices and beyond. By combining Soitec’s Smart Cut technology and engineered substrate expertise with Freescale’s advanced CMOS process capabilities, the development team was able to produce the industry’s first functional 45nm CMOS devices on bonded strained SOI substrates.

To satisfy CMOS integration requirements for tomorrow’s high performing chips, Soitec and Freescale worked in close cooperation to optimize the critical relationship between the transistor architecture and the strained SOI substrate.

The initial work performed was based on silicon germanium-on-insulator, followed by sSOI, allowing both Soitec and Freescale to learn how to match a strained SOI substrate with a device design to optimize the technology applications and outcome. sSOI is a strong candidate for the sub-65-nm technology nodes due to its unique ability to address high-performance, low-power-consumption applications.

NMOS device results on strained SOI exhibited a mobility increase of approximately 70%. Electrical reliability data showed no difference between standard SOI and sSOI devices. Furthermore, no relaxation of the strained silicon was observed at 40nm transistor geometries. The ability to produce strained silicon with thicknesses above 40nm makes sSOI highly compatible with existing SOI CMOS processes.

SOI material, which incorporates a layer of silicon on an embedded layer of silicon dioxide, enables chips built on the substrate to function at significantly higher speeds with less electrical loss – enabling a two to three times reduction in power consumption, and a 20% to 30% improvement in device speed. Similarly, strained silicon allows electrons to experience less resistance and flow faster, resulting in a 20% to 30% increase in transistor performance. Combining these technologies, in the form of strained SOI material, will enable Freescale to realize the cumulative benefits of both technologies, permitting significant advances in device speed, power consumption and integrated circuits (IC) packing density.

Device results reveal an approximate 70% increase in electron mobility, as well as high compatibility with existing SOI CMOS processes, the collaborative effort demonstrated that 45nm CMOS devices built using strained SOI substrates can effectively take device performance to the next level – ultimately enabling Freescale to bring faster, more power-efficient next-generation chips to market.