Taiwan Semiconductor Manufacturing Company said it had successfully completed the first of three CyberShuttle prototype production runs for the company’s 65nm Nexsys Technology for System-on-Chips (SoC). According to the company’s statement, it has tested production of chips by five of its major customers as well as some other clients.

“The launch of the foundry industry’s first production prototype runs at the 65nm node realizes our commitment to make the Nexsys 65nm process available by the end of 2005,” said Jason Chen, vice president of corporate development at TSMC.

Among the companies aboard this first run are Altera, Broadcom, and Freescale, TSMC said.

The prototype launch opens the doors to 65nm prototyping work. Two more 65nm prototype shuttles will be launched by the end of 2005, and will include the Low Power, General Purpose and other enhancement process options. Bookings for all three shuttles are strong. Beginning in 2006, TSMC will launch additional 65nm shuttles every other month, enabling customers and EDA, IP and library suppliers to prototype and qualify their leading-edge designs.

The new technology features a minimum number of process changes, such as strained silicon and a new nickel silicide, to shorten time to volume. The 65nm Nexsys technology is the third-generation TSMC process to employ low-k dielectrics and the fourth generation to use copper interconnects.

The 65nm process may be the first-generation process to use immersion lithography techniques, developed in partnership between TSMC and ASM Lithography. TSMC took delivery of the first production-worthy 193nm immersion lithography system in 2004. Capable of 132nm wavelengths, the 193nm immersion system also provides a greater than 200% depth-of-field improvement versus dry lithography systems. The new 65nm process will be implemented in TSMC’s 300mm manufacturing facilities, Fab 12 and Fab 14.

In response to customer demand, TSMC’s first 65nm Nexsys technology, which will enter first production in December 2005, is optimized for low power. A high-speed version will be available in 2006, followed later in the year by a general-purpose 65nm process. A version employing SOI technology and an ultra-high-speed version will be introduced in 2007. Logic and mixed-signal options are slated for all versions, with embedded memory available in each.