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United Microelectronics Corp., a contract semiconductor foundry, and Cadence Design Systems, have announced the readiness of UMC;s 65nm process technology for X architecture-based chip designs. Theoretically, this means that UMC will be able to produce cost-effective high-speed chips or system-on-chip (SoC) devices.

“UMC has been working with Cadence for several years to bring the advantages of the X architecture to mainstream SoC designers. We are delighted to extend our readiness of this technology to the 65nm generation, as leading customers can now leverage the X Architecture with the industry’s most advanced process technology to increase the competitiveness of their products,” said Patrick T. Lin, chief SoC architect at UMC.

The X Architecture is a new approach to chip design whereby diagonal interconnects are employed to reduce chip costs, increase performance and lower power consumption. Targeted at chips with five or more metal layers, the X Architecture rotates the primary direction of the interconnect in the fourth and fifth metal layers by 45 degrees in relation to conventional orthogonal, or “Manhattan”, architecture. Layers one through three remain unchanged, preserving the design community’s investment in existing cell libraries, memory cells, memory compilers, datapath compilers, and IP hard cores. In addition, the X Architecture allows 45 degrees “wrong-way jogs”, which provides an additional four degrees of freedom in each layer of routing.

Cadence and UMC have qualified 65nm X architecture design rules, the Cadence X architecture, and design support manual (DSM) documents, allowing fabless and IDM companies to leverage the cost and performance benefits of the X Architecture for their leading system-on-chip (SoC) designs. The two companies are engaging with mutual customers towards X Architecture production designs at leading process nodes.

The Cadence X Architecture is now available to customers for UMC's 130nm, 90nm and 65nm process technologies.

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