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Taiwan Semiconductor Manufacturing Co. (TSMC) reportedly plans to offer its customers among logic chip designers 55nm process technology in Q2 2007. While it is unclear whether the 55nm fabrication tech is the so-called optical shrink of the 65nm manufacturing process, it is known that TSMC will offer the new manufacturing option to chipsets and graphics processors developers.

The launch of thinner – 55nm – process technology will allow TSMC to outstrip rivals in Q2 2007 and receive orders for lucrative chips that usually contain hundreds of millions of transistors. It is uncertain whether 55nm is a derivative of 65nm process technology, but if it is, TSMC’s customers may relatively quickly adopt it, as it should use similar, if not the same, design libraries. Potentially, this will allow developers of large chips to shrink their sizes and thus manufacturing costs.

According to China Economic News Service (CENS) agency, TSMC is already shipping silicon wafers made using 80nm fabrication process to customers, including chipsets and graphics processing units (GPUs) designers ATI Technologies and Nvidia Corp. The news-agency also claims that “they expect the 65nm process technology to enter into volume production next quarter”, with Qualcomm, Freescale Semiconductor and Altera to “also” adopt the process.

Even though both ATI and Nvidia are expected to use 65nm and 80nm process technologies, none of those two companies indicated utilization of 55nm manufacturing process in the foreseeable future.

TSMC will also begin the pilot production of low-power 55nm process in the third quarter next year, according to the report.


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