PCI-SIG, the special interest group responsible for PCI Express industry-standard I/O technology, said that the final version of 2.0 specification is available. The improved input/output technology provides higher bandwidth as well as some other features required by the upcoming generations of hardware.

“In today’s world, applications are becoming more advanced and are requiring more bandwidth. This is the perfect time to release PCIe 2.0, which not only supports high-bandwidth applications such as high-end graphics, but also adds many new architectural enhancements,” said Al Yanes, PCI-SIG chairman and president.

The main difference between PCI Express 1.0a, 1.1 and 2.0 is higher transfer speed – 5GHz compared to 2.5GHz on spec 1.0a and 1.1 – and improved bandwidth, which is now 16GB/s for 16-lane link.

In addition to the faster signaling rate, PCI-SIG working groups also added several new protocol layer improvements to the PCI Express base 2.0 specification which will allow developers to “design more intelligent devices to optimize platform performance and power consumption while maintaining interoperability, low cost and fast market introduction”. These architecture improvements include:

• Dynamic link speed management allows developers to control the speed at which the link is operating;
• Link bandwidth notification alerts platform software (operating system, device drivers, etc) of changes in link speed and width;
• Capability structure expansion increases control registers to better manage devices, slots and the interconnect;
• Access control services allows for optional controls to manage peer-to-peer transactions;
• Completion timeout control allows developers to define a required disable mechanism for transaction timeouts;
• Function-level reset provides an optional mechanism to reset functions within a multi-function device;
• Power limit redefinition enables slot power limit values to accommodate devices that consume higher power.