At the first day of its annual technology forum, Intel Corp. demonstrated the first working chips made using 32nm process technology. Even though such chips cannot perform any operations, they showcase Intel’s ability to make them and once again assures that the company is on-track to produce commercial processors utilizing 32nm process technology in two years time.

Paul Otellini, chief executive of Intel Corp., showed the world’s first 300mm wafer built using next-generation 32nm process technology. Intel’s 32nm test chips incorporate logic and memory (static random access memory, SRAM) to house more than 1.9 billion transistors. Besides demonstrating the wafer, Mr. Otellini showed the industry’s first working chips built using 32nm technology. The 32nm process uses the company’s second-generation high-k and metal gate transistor technology and is projected to be commercially used in 2009..

The development of advanced test chips serves as a critical milestone in the company’s march toward high-volume manufacturing of 32nm process technology. With plans to introduce processors built on 32nm technology in 2009, in case of success, Intel will maintain its industry lead delivering the most advanced manufacturing technologies.

The wafer demonstration at Intel Developer Forum (IDF) is a yet another time when Intel reaffirms its clients and investors that it is able to start 32nm production in 2009. Due to very thin structures of transistors in case of 32nm process technology, special – extreme ultraviolet lithography – tools are needed for appropriate production. The main idea of extreme ultraviolet lithography is ability to “draw” substantially finer circuits on wafers when making chips than it is possible today.

EUV lithography is positioned for commercial deployment in 2009, but several issues were needed to be addressed to keep the technology on track. A key issue confronting the commercialization efforts of EUV lithography is the ability to increase source output power to meet the wafer throughput requirements of high volume manufacturing, while minimizing the cost of ownership for EUV lithography tools. Another issue with EUV lithography is requirement for extremely precise mirrors.