Intel Corp. said that it had completed the development phase of its next-generation manufacturing process that further shrinks chip circuitry to 32nm. The company reiterated that it was on track for production readiness of this future generation using even more energy-efficient, denser and higher performing transistors in the fourth quarter of 2009.
"Our manufacturing prowess and resulting products have helped us widen our lead in computing performance and battery life for Intel-based laptops, servers and desktops. As we've shown this year, the manufacturing strategy and execution have also given us the ability to create entirely new product lines for MIDs, CE equipment, embedded computers and netbooks , " said Mark Bohr, Intel Senior Fellow and director of process architecture and integration.
Intel will provide a multitude of technical details around the 32nm process technology along with several other topics during presentations at the International Electron Devices meeting (IEDM) next week in San Francisco, California.
Intel’s 32nm manufacturing process utilizes the company’s second-generation, high-k/metal gate technology, a strained channel, and nine levels of low-k interconnect dielectrics, according to previously released information that cites an Intel’s document available from IEDM’s web-site on request. The process enables the highest drive currents reported to date for 32nm technology: NMOS saturated drive current is 1.55mA/micron while the corresponding PMOS value is 1.21mA/micron.
Intel’s 32nm test chips incorporate logic and memory (static random access memory, SRAM) to house more than 1.9 billion transistors with 4.2Mb² array density. The chip features 0.171 micron² cell size. The process evaluation chip reportedly functioned at 3.80GHz with 1.1V voltage.