Taiwan Semiconductor Manufacturing Company this week admitted issues it experienced with the 40nm production process, said that it would double the 40nm output by the end of the year and also pledged to start making 22nm chips in 2012.
160 Thousand Wafers at 40nm Node by Year End
The migration to 40nm process technology has been pretty tough for Taiwan Semiconductor Manufacturing Company. On the one hand, there are only a handful of companies in the world, who really need such advanced fabrication technology, on the other hand, the demand for 40nm capacity turned out to be much stronger than the company initially anticipated, which is why the supply is now constrained by the lack of equipment at TSMC, not yields, as it used to be.
“At this stage we only have fab 12 ready to tape production of 40nm and we are able to do about 80 000 wafers per quarter at the moment. These are 300mm wafers. And this will be doubled by the end of this year, to 160 000 300mm wafers for 40nm capacity by the end of this year, and partly from fab 12 and partly from fab 14,” said Shang-Yi Chiang, senior vice president of R&D at TSMC at TSMC Japan Executive Forum in Yokohama, reports EETimes web-site.
Challenges with 40nm Kill 32nm Process
Moving to 40nm fabrication process was challenging by itself: TSMC had to use the new tools along with new materials, hence, the yields were below original expectations.
“Moving to 45nm and 40nm nanometer is a lot more challenging. This is the first time we began to use 193nm shrink immersion. That means the photo resist during exposure will be merged in water and is a very high potential defect. For this a very big challenge. We began to develop the third generation. We began to use the second generation low k material with a k value of 2.5 and at this k value the material become quite fragile so there is a lot of potential issues in the package side,” said Mr. Chiang.
The senior vice president of research and development at TSMC did not mention the 32nm fabrication process – which was supposed to use 193nm shrink immersion lithography and silicon oxinitride/poly (SiON/Poly) dielectrics – throughout the whole conference, therefore, it is more than likely that the technology has been cancelled due to potentially even worse problems that the company experienced with the 40nm process.
28nm On Track with the Roadmap
Instead of 32nm fabrication process, TSMC concentrates on 28nm technologies. Initially the company plans to launch 28nm SiON/Poly process for low-power devices and later on it will roll-out high-k metal gate (HKMG) based technologies for more advanced products.
“The first node we are going to release for the 28nm will be called the 28LP. This is our poly gate and silicon oxide nitrate version. We will establish production at the end of June this year, about four months from now, and this is for the low power application. […] The first HKMG process we call 28HP for the high performance application will be introduced by the end of September this year, and followed by three months later December will be the 28HPL, which is [our] first high-k metal gate introduction for the low power application,” said Mr. Chiang.
22nm: The Next Leap
The industry will have to stick to 28nm and 40nm fabrication processes for quite some time: only in the second half of 2012 TSMC plans to introduce its 22nm fabrication process. In the meantime, the world’s largest contract manufacturer of semiconductors will have to ensure that its yields, services and performance are better compared to those offered by Globalfoundries, which – together with IBM – has tremendous experience in developing advanced fabrication processes and a lot of money to acquire new equipment.
“Going forward, we plan to introduce 22nm node about two years after we introduce 28nm. The first introduction would likely be in the Q3 of 2012 for the high performance version and followed by the low power version in about the end of Q1 2013. Going to 22nm and beyond, we would like two models to be introduced. Firstly, we will go to the second generation high-k metal gate. We will continue using the 193nm immersion with double patterning in the early stage, and [secondly] we will migrate to EUV or multiple e-beam direct write if one of these technologies can be more mature and more cost effective,” concluded Mr. Chiang.