Samsung: 20nm Chips Will Feature Up to 12 Billion of Transistors[02/23/2011 10:35 PM]
Samsung Electronics, a major maker of consumer electronics, memory and various semiconductors, said on Wednesday that later this year it would start test production of chips using 20nm process technology. The company will offer its foundry customers test shuttles in the second half of the year. So far Samsung is the first foundry provider to promise test of 20nm in 2011.
"Our 20nm technology will be a full node shrink from 28nm, enabling the ~50% area scaling that the industry has come to expect with each technology generation. The technology has been designed to allow us to maintain our leadership in die size and cost, which remain critical factors for customers at leading-edge nodes. [...] Test-chip shuttles for customers will begin in the second half of this year," said Ana Hunter, vice president of Samsung’s North American foundry services, in a blog post.
Samsung's 20nm process technology will use second-generation gate last high-K metal gate (HKMG) process technology as well as fifth-generation strained silicon wafers. In addition, the fabrication process will utilize second-generation ultra-low k dielectrics to lower power dissipation by reducing interconnect capacitance and wiring delay. Samsung also plans to change local interconnect and self-aligned vias to achieve cell-level scaling and elimination of a metal layer. Finally, 193nm immersion lithography will be supplemented by source-mask optimization constrained minimum pitch to reduce the need for time-consuming, costly double-patterning.
Actual commercial chips made using 20nm process technologies are years away, but there are interesting assumptions that Samsung makes about them. The largest chips produced using 40nm fabrication process incorporate from two to three billion of transistors; chips made at 28nm node are projected to integrate already four to six billion; and processors manufactured utilizing 20nm technology will be able to pack in eight to twelve billion of elements. In general, this means that performance of chips due in 2013 - 2014 will be at least three times higher compared to those available today. In reality, performance leaps can be much greater in certain applications as chip designers rebalance their products to better match demands of tomorrow's applications. Alternatively, process technology shrink means that power consumption of devices comparable to today's will decrease by several times in the coming years.
"The 20nm technology is ideally suited for a broad range of high performance and power-sensitive devices, including chips designed for smartphones, tablets, other portable consumer electronics as well as IT communications infrastructure," noted Ms. Hunter.
It is noteworthy that Samsung Electronics, the company that is not a leader in the foundry business, became the first to promise 20nm test shuttles in the latter half of the year. Globalfoundries, one of the largest contract makers of semiconductors, plans to start risk production using 20nm/22nm in late 2012, but the company has never disclosed when does it plan to start offering test shuttles for 20nm and 22nm chips.
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