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Even though PCI Express 3.0 is still several months away, PCI Express 4.0 is already in the works and some basic specifications of the interconnection technologies are already known. The maximum bandwidth of the fourth generation of PCIe interconnect will be 16GT/s per lane. There will also be a number of new features implemented.

"The initial report we got yesterday is a PCI Express 4.0 is feasible - we have to work out the details, but it is feasible," said Al Yanes, president of the PCI SIG, reports EETimes.

The group, which leads the development, includes AMD, Hewlett-Packard, IBM and Intel. It is reported that the companies are already conducting simulations using chip, channel, packet and socket data. Currently they reportedly expect to achieve speed of at least whopping 16GT/s per lane (which means 256Gb/s [32GB/s] bandwidth for PCI Express x16 slots). The target speed spec is projected to be delivered by the end of 2011.

PCI Express 4.0 will continue to use copper wires, which is logical, given the fact that changing technology process for making graphics cards, mainboards and other devices is hardly economically feasible. Still, it will likely require new kind of manufacturing process and new materials while still maintaining backwards compatibility. That is a big shift for the PCIe community which has not previously required major changes of board makers, according to EETimes.

PCIe 4.0 will probably be limited to distances of about 8 to 12 inches compared to 20 inches for PCI Express 3.0. It is noteworthy, though, that it took PCIe 3.0 four years to get developed with 8Gb/s speed.

"We think we can eke out one more turn of the crank out of copper, so we are not looking at optics yet," said Ramin Neshanti, chairman of the PCI SIG's serial communications working chair.

Tags: PCI Express, AMD, Intel, IBM, Nvidia

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Discussion started: 06/27/11 07:07:10 AM
Latest comment: 06/27/11 03:17:57 PM
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We'll need a completely new QPI and HyperTransport for that. Both offer 12.8 GiB/s in each direction at 3.2 GHz, which means even PCI-E 3.0 will be limited (almost 16 GiB/s in each direction with 16 lanes), at least with multi-GPU configurations.
0 0 [Posted by: Harry Lloyd  | Date: 06/27/11 07:07:10 AM]
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quit a lot of the PCI-e traffic is point to point, meaning it doesn't involve the CPU at all, and therefore doesn't involve the HT or QPI links either.
0 1 [Posted by: Countess  | Date: 06/27/11 03:17:57 PM]
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