Samsung Electronics, a major consumer electronics maker and a contract maker of semiconductors, this week announced that it had successfully taped-out a test chip based on its 20nm process technology with high-K metal gate. The test chip includes microprocessor IP from ARM and is supposed Samsung and its customers to better understand peculiarities of 20nm fabrication process.
At the 20nm process, an entirely new design infrastructure approach is needed to address impediments in developing and manufacturing next-generation, energy-efficient SoCs. Many new 20nm design kits, router and other design enablement features were used in this first test chip to support novel process innovations such as new device structures, local interconnects, and advanced routing rules.
Samsung's 20nm process technology will use second-generation gate last high-K metal gate (HKMG) process technology as well as fifth-generation strained silicon wafers. In addition, the fabrication process will utilize second-generation ultra-low k dielectrics to lower power dissipation by reducing interconnect capacitance and wiring delay. Samsung also plans to change local interconnect and self-aligned vias to achieve cell-level scaling and elimination of a metal layer. Finally, 193nm immersion lithography will be supplemented by source-mask optimization constrained minimum pitch to reduce the need for time-consuming, costly double-patterning.
Samsung used ARM physical and processor IP to validate the design readiness of their most advanced node. ARM provided a full implementation of the test chip, which contained an ARM Cortex-M0 processor, ARM Artisan prototype libraries (both 12-track high performance and 9-track high density versions), custom memories, GPIO, and test structures. This comprehensive implementation provided a solid proof point of the silicon characteristics attainable Samsung’s advanced 20nm process. Actual commercial chips made using 20nm process technologies are years away, the test chips are only one of the first steps towards commercialization of a process technology.
Samsung utilized both the Cadence unified digital design flow and the Synopsys Galaxy implementation platform to implement different components of the test chip in order to validate Samsung’s design methodology for both Cadence and Synopsys design flows.
Samsung Foundry’s 20nm early access process design kit (PDK) is currently available to those customers who are in the initial stages of designing their next-generation products.
“With more functionality converged into a single device, semiconductor SoC design companies need advanced foundry services that provide comprehensive design enablement portfolios along with proven manufacturing technologies. This is a significant milestone with regards to the design ecosystem that needs to be developed in parallel with the manufacturing process. The design methodology, tools and IPs used on this 20nm test chip bring together the most advanced technology from our design infrastructure partners together with Samsung process and design technology to solve critical design challenges so our customers can deliver their latest chips to market quickly and efficiently," said. Kyu-Myung Choi, vice president of system LSI infrastructure design center of device solutions division at Samsung Electronics.