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Samsung Electronics on Thursday said that it reached another milestone in the development of 14nm FinFET process technology with the successful tape-out of multiple development vehicles, including ARM Cortex-A7 test chip, in collaboration with its key design and IP partners. In addition, Samsung has signed an agreement with ARM for 14nm physical IP and libraries.

Samsung Tapes Out ARM Cortex-A7, Near Threshold Voltage Chip on 14nm Process Tech

As part of its 14nm FinFET development process, Samsung, and its ecosystem partners – ARM, Cadence, Mentor and Synopsys – taped out multiple test chips ranging from a full ARM Cortex-A7 processor implementation to a SRAM-based chip capable of operation near threshold voltage levels as well as an array of analog IP.

The full ARM Cortex-A7 processor test chip tape-out represents a significant milestone for silicon manufacturing for the fabless ecosystem. The Cortex-A7 implementation on FinFET demonstrates the low-power component of the ARM big.Little processor configuration/technology strategy for mobile computing platforms. The Samsung 14nm FinFET enablement for system-on-chip (SoC) design provides improved leakage and dynamic power advantages to the expanding mobile computing market. Enabling SoC design on FinFET allows the continued fast pace of innovation that is the hallmark of the mobile market segment.

“The design complexities at 14nm require complete harmony between the process technology, design methodology, tools and IPs. We are synchronizing all the key elements so our customers can deliver their newest chips to market quickly and efficiently,” said Kyu-Myung Choi, senior vice president of system LSI infrastructure design center at device solutions division at Samsung Electronics.

Samsung Details 14nm FinFET Test Chips

The Cortex-A7 processor test chip was implemented by Cadence in collaboration with ARM and Samsung. Cadence delivered a full RTL-to-signoff flow, building upon a tool set that has been thoroughly tested on 20nm designs requiring automated double patterning. The tight collaboration with Samsung and ARM enabled Cadence to hone its technology for 14nm FinFET designs, paving the way for 14nm market readiness. ARM used Cadence tools to develop the 14nm FinFET libraries, and Cadence tools were also used for a full-flow RTL-to-signoff tapeout of the processor core on Samsung’s 14nm FinFET process, as well as chip-level integration and verification.

Samsung used Synopsys tools optimized for FinFET devices to implement additional IP on this vehicle, including low power SRAMs intended to operate with the power supply close to threshold voltage levels. The move from two-dimensional transistors to three-dimensional transistors introduces several new IP and EDA tool challenges including modeling. The multi-year collaboration between Samsung and Synopsys has delivered foundational modeling technologies for 3D parasitic extraction, circuit simulation and physical design-rule support of FinFET devices.

Samsung is also extending their work with Mentor to enable a complete solution at 14nm FinFET that addresses customer challenges in design, validation, manufacturing co-optimization, and post-design production ramps. The collaborative efforts leverage the unique capabilities of Samsung’s processes, while helping designers deal with the complexities of multi-patterning lithography, FinFET transistors, and more complex reliability requirements.

14nm FinFET Process Design Kit Available

With its process design kit available to customers today, customers can start designing with models, design rule manuals and technology files that have been developed based on silicon results from previous 14nm FinFET test chips run in Samsung’s R&D facilities. This PDK includes design flows, routers and other design enablement features to support new device structures, local interconnects, and advanced routing rules. The investments that Samsung is making into the entire ecosystem at 14nm will give customers early access to all elements of the design infrastructure to accelerate their chip development, but Samsung does not indicate when it plans to start manufacturing using 14nm FinFET manufacturing tech.

Tags: Samsung, 14nm, FinFET, Semiconductor, ARM, Cortex


Comments currently: 9
Discussion started: 12/21/12 05:46:18 AM
Latest comment: 03/09/16 12:36:35 AM
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This is rather impressive, as it suggests that Samsung SC manufacturing technology lags Intel by less than a full node, in contrast to the other competitors, who are more than one behind.
For Intel, this is not good news, as Samsung, unlike Intel, can apply its technology directly to in house produced end products such as tablets and smart phones.
That suggests Samsung can capture more of the value added in the larger electronics product market, just as Intel used to in the PC space with the 386 tax, but which Intel cannot in the smart phone competition because of ARM.
1 1 [Posted by: etudiant  | Date: 12/21/12 05:46:18 AM]

Good but not impressive. This is just a TAPE-OUT announcement not a successful fabrication of the design. I would be very impressed if any company right now (other than Intel) has reached a NEAR commercially-viable yield level for 22nm or smaller nodes. As much as I hate to say it, but Intel is way ahead of the competition in process technology. Intel has previously announced that its engineers have actual next generation 14nm processors physically under test in their labs. Other players still struggle to move beyond the 28nm node.
2 0 [Posted by: texasti  | Date: 12/21/12 11:26:01 AM]

Intel makes lots of claims that often don't pan out. Ivy Bridge is a perfect example of lots of hype and a poor FinFET design that limited IB's potential so much Intel has completely abandon that particular FinFET design. But when Intel was tyring to sell IB as the second coming of Christ, they didn't tell the truth or the whole usual.

Being first isn't always being best, as Intel has demonstrated. It's also acknowledge that smaller node sizes now days means lower power consumption but not necessarily higher performance processors. Being one node behind is not a significant disadvanateg, especially when those who are "behind" bring a better, more mature process and processor that has excellent performance and lower power consumption.
1 2 [Posted by: beenthere  | Date: 12/21/12 01:39:20 PM]
- collapse thread


IB was only meant to be a tick (just a shrink for SB design layout) using the first generation transistor structure developed for the new 22nm process. To me, the process has delivered quite well given that its the first ever FinFET design introduced for mainstream consumers. A reduction of over 20% in power consumption for 5-10% increase in performance is great for a new shrink. Now the great potential of Intel's 22nm FinFET will be utilized by Haswell which is not only a new architecture, but also very optimized for this particular advanced process. Also, Intel has already stated during last IDF that the Haswell chips will be manufactured using a different transistor structure, the second generation of 22nm process. That what enables the engineers at Intel to push the power envelope of Core processors into the sub-10W territory. I'm very excited about the new sub-10w chips.
0 0 [Posted by: texasti  | Date: 12/22/12 03:32:36 PM]
You mean a tock?
0 0 [Posted by: fanboyslayer  | Date: 12/24/12 06:17:57 AM]


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